74 lines
2.3 KiB
C
74 lines
2.3 KiB
C
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/*******************************************************************************
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* File Name: cycfg_peripherals.c
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*
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* Description:
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* Peripheral Hardware Block configuration
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* This file was automatically generated and should not be modified.
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* Device Configurator: 2.0.0.1483
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* Device Support Library (../../../psoc6pdl): 1.3.1.1499
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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********************************************************************************/
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#include "cycfg_peripherals.h"
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const cy_stc_scb_uart_config_t CYBSP_UART_config =
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{
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.uartMode = CY_SCB_UART_STANDARD,
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.enableMutliProcessorMode = false,
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.smartCardRetryOnNack = false,
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.irdaInvertRx = false,
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.irdaEnableLowPowerReceiver = false,
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.oversample = 8,
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.enableMsbFirst = false,
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.dataWidth = 8UL,
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.parity = CY_SCB_UART_PARITY_NONE,
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.stopBits = CY_SCB_UART_STOP_BITS_1,
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.enableInputFilter = false,
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.breakWidth = 11UL,
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.dropOnFrameError = false,
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.dropOnParityError = false,
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.receiverAddress = 0x0UL,
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.receiverAddressMask = 0x0UL,
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.acceptAddrInFifo = false,
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.enableCts = false,
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.ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
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.rtsRxFifoLevel = 0UL,
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.rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
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.rxFifoTriggerLevel = 0UL,
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.rxFifoIntEnableMask = 0UL,
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.txFifoTriggerLevel = 63UL,
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.txFifoIntEnableMask = 0UL,
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};
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#if defined (CY_USING_HAL)
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const cyhal_resource_inst_t CYBSP_UART_obj =
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{
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.type = CYHAL_RSC_SCB,
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.block_num = 5U,
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.channel_num = 0U,
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};
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#endif //defined (CY_USING_HAL)
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void init_cycfg_peripherals(void)
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{
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Cy_SysClk_PeriphAssignDivider(PCLK_SCB5_CLOCK, CY_SYSCLK_DIV_16_BIT, 0U);
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#if defined (CY_USING_HAL)
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cyhal_hwmgr_reserve(&CYBSP_UART_obj);
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#endif //defined (CY_USING_HAL)
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}
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