48 lines
1.7 KiB
C
48 lines
1.7 KiB
C
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/*******************************************************************************
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* File Name: cycfg_clocks.c
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*
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* Description:
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* Clock configuration
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* This file was automatically generated and should not be modified.
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* Device Configurator: 2.0.0.1483
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* Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.5.0.1837
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*
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********************************************************************************
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* Copyright 2017-2019 Cypress Semiconductor Corporation
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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********************************************************************************/
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#include "cycfg_clocks.h"
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#if defined (CY_USING_HAL)
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const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
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{
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.type = CYHAL_RSC_CLOCK,
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.block_num = CYBSP_CSD_CLK_DIV_HW,
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.channel_num = CYBSP_CSD_CLK_DIV_NUM,
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};
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#endif //defined (CY_USING_HAL)
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void init_cycfg_clocks(void)
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{
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Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
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Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
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Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
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#if defined (CY_USING_HAL)
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cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
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#endif //defined (CY_USING_HAL)
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}
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