This file contains invisible Unicode characters that are indistinguishable to humans but may be processed differently by a computer. If you think that this is intentional, you can safely ignore this warning. Use the Escape button to reveal them.
/**
@page EEPROM_Emulation application to show an eeprom emulation
@verbatim
******************************************************************************
* @file EEPROM/EEPROM_Emulation/readme.txt
* @author MCD Application Team
* @brief Description of the EEPROM_Emulation application.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@endverbatim
@par Application Description
This application shows how to emulate EEPROM on internal flash.
Please refer to AN3969 for further details regarding this application.
NUCLEO-F746ZG board Rev.B LEDs can be used to monitor the application status:
- LED2 is On when the application runs successfully.
- LED2 is toggle in case of error.
@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
@note The application needs to ensure that the SysTick time base is always set to 1 millisecond
to have correct HAL operation.
@par Keywords
EEPROM, Emulation, Flash, Program, Erase, Sectors, OPCODE
@NoteIf the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors,
then it is highly recommended to enable the CPU cache and maintain its coherence at application level.
The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes).
@Note It is recommended to enable the cache and maintain its coherence, but depending on the use case
It is also possible to configure the MPU as "Write through", to guarantee the write access coherence.
In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable.
Even though the user must manage the cache coherence for read accesses.
Please refer to the AN4838 “Managing memory protection unit (MPU) in STM32 MCUs”
Please refer to the AN4839 “Level 1 cache on STM32F7 Series”
@par Directory contents
- EEPROM/EEPROM_Emulation/Inc/stm32f7xx_hal_conf.h HAL Configuration file
- EEPROM/EEPROM_Emulation/Inc/main.h Header for main.c module
- EEPROM/EEPROM_Emulation/Inc/eeprom.h Header for eeprom.c module
- EEPROM/EEPROM_Emulation/Inc/stm32f7xx_it.h Header for stm32f7xx_it.c
- EEPROM/EEPROM_Emulation/Src/main.c Main program
- EEPROM/EEPROM_Emulation/Src/eeprom.c EEPROM program
- EEPROM/EEPROM_Emulation/Src/stm32f7xx_it.c Interrupt handlers
- EEPROM/EEPROM_Emulation/Src/system_stm32f7xx.c STM32F7xx system clock configuration file
@par Hardware and Software environment
- This application runs on STM32746ZG device.
- This application has been tested with NUCLEO-F746ZG Rev.B board and can be
easily tailored to any other supported device and development board.
@par How to use it ?
In order to make the program work, you must do the following :
- Open your preferred toolchain
- Rebuild all files and load your image into target memory
- Run the application
*/
767d083e20