87 lines
3.8 KiB
Plaintext
87 lines
3.8 KiB
Plaintext
/**
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@page RNG_MultiRNG Multiple Random Numbers Generator example
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@verbatim
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******************************************************************************
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* @file RNG/RNG_MultiRNG/readme.txt
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* @author MCD Application Team
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* @brief Description of multiple random numbers generation example.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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@endverbatim
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@par Example Description
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Configuration of the RNG using the HAL API. This example uses the RNG to generate 32-bit long random numbers.
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At the beginning of the main program the HAL_Init() function is called to reset
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all the peripherals, initialize the Flash interface and the systick.
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Then the SystemClock_Config() function is used to configure the system
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clock (SYSCLK) to run at 216 MHz.
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The RNG peripheral configuration is ensured by the HAL_RNG_Init() function.
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The latter is calling the HAL_RNG_MspInit() function which implements
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the configuration of the needed RNG resources according to the used hardware (CLOCK,
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GPIO, DMA and NVIC). You may update this function to change RNG configuration.
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After startup, user is asked to press User push-button.
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The 8-entry array aRandom32bit[] is filled up by 32-bit long random numbers
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at each key press.
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The random numbers can be displayed on the debugger in aRandom32bit variable.
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In case of error, LED3 is toggling at a frequency of 1Hz.
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@par Keywords
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Analog, RNG, Random, FIPS PUB 140-2, Analog Random number generator, Entropy, Period
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@Note If the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors,
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then it is highly recommended to enable the CPU cache and maintain its coherence at application level.
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The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes).
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@Note It is recommended to enable the cache and maintain its coherence, but depending on the use case
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It is also possible to configure the MPU as "Write through", to guarantee the write access coherence.
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In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable.
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Even though the user must manage the cache coherence for read accesses.
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Please refer to the AN4838 “Managing memory protection unit (MPU) in STM32 MCUs”
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Please refer to the AN4839 “Level 1 cache on STM32F7 Series”
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@par Directory contents
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- RNG/RNG_MultiRNG/Inc/stm32f7xx_hal_conf.h HAL configuration file
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- RNG/RNG_MultiRNG/Inc/stm32f7xx_it.h Interrupt handlers header file
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- RNG/RNG_MultiRNG/Inc/main.h Header for main.c module
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- RNG/RNG_MultiRNG/Src/stm32f7xx_it.c Interrupt handlers
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- RNG/RNG_MultiRNG/Src/main.c Main program
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- RNG/RNG_MultiRNG/Src/stm32f7xx_hal_msp.c HAL MSP module
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- RNG/RNG_MultiRNG/Src/system_stm32f7xx.c STM32F7xx system source file
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@par Hardware and Software environment
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- This example runs on STM32F722xx/STM32F723xx/STM32F732xx/STM32F733xx devices.
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- This example has been tested with STM32F722ZE-Nucleo board and can be
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easily tailored to any other supported device and development board.
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@par How to use it ?
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In order to make the program work, you must do the following:
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- Open your preferred toolchain
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- Rebuild all files and load your image into target memory
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- Run the example
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*/
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