/**
@page QSPI_ReadWrite_IT QSPI Read/Write in interrupt mode example
@verbatim
******************************************************************************
* @file QSPI/QSPI_ReadWrite_IT/readme.txt
* @author MCD Application Team
* @brief Description of the QSPI Read/Write in interrupt mode example.
******************************************************************************
* @attention
*
* Copyright (c) 2018 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@endverbatim
@par Example Description
How to use a QSPI memory in interrupt mode.
This example describes how to erase a part of a QSPI memory, write data in Interrupt mode, read data
in interrupt mode and compare the result in an infinite loop.
In this example, the code is executed from internal flash while data are in internal SRAM memory.
LED1 is turned on as soon as the comparison is successful.
The code enter a infinite while loop as soon as a comparison error occurs or an error is returned by HAL API.
In this example, HCLK is configured at 216 MHz.
@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
based on a variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
than the peripheral interrupt. Otherwise, the caller ISR process will be blocked.
To change the SysTick interrupt priority you have to use the HAL_NVIC_SetPriority() function.
@note The application needs to ensure that the SysTick time base is always set to 1 millisecond
to have correct HAL operation.
@par Keywords
Memory, QUADSPI, Erase, Read, Write, Interrupt
@Note<74>If the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors,
<20><><A0><A0><A0>then it is highly recommended to enable the CPU cache and maintain its coherence at application level.
<0A><><A0><A0><A0><A0>The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes).
@Note It is recommended to enable the cache and maintain its coherence, but depending on the use case
<0A><><A0><A0><A0> It is also possible to configure the MPU as "Write through", to guarantee the write access coherence.
<0A><><A0><A0><A0><A0>In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable.
<0A><><A0><A0><A0><A0>Even though the user must manage the cache coherence for read accesses.
<0A><><A0><A0><A0><A0>Please refer to the AN4838 <20>Managing memory protection unit (MPU) in STM32 MCUs<55>
<0A><><A0><A0><A0><A0>Please refer to the AN4839 <20>Level 1 cache on STM32F7 Series<65>
@par Directory contents
- QSPI/QSPI_ReadWrite_IT/Inc/stm32f7xx_hal_conf.h HAL configuration file
- QSPI/QSPI_ReadWrite_IT/Inc/stm32f7xx_it.h Interrupt handlers header file
- QSPI/QSPI_ReadWrite_IT/Inc/main.h Header for main.c module
- QSPI/QSPI_ReadWrite_IT/Src/stm32f7xx_it.c Interrupt handlers
- QSPI/QSPI_ReadWrite_IT/Src/main.c Main program
- QSPI/QSPI_ReadWrite_IT/Src/system_stm32f7xx.c STM32F7xx system source file
- QSPI/QSPI_ReadWrite_IT/Src/stm32f7xx_hal_msp.c HAL MSP file
@par Hardware and Software environment
- This example runs on STM32F750xx devices.
- This example has been tested on STM32F7508-DISCOVERY board and can be
easily tailored to any other supported device and/or development board.
- STM32F7508-DISCOVERY Set-up :
- Board is configured by default to access QSPI memory
@par How to use it ?
In order to make the program work, you must do the following :
- Open your preferred toolchain
- Rebuild all files and load your image into target memory
- Run the example
*/
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