130 lines
7.1 KiB
Plaintext
130 lines
7.1 KiB
Plaintext
/**
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@page EEPROM_Emulation application to show an eeprom emulation
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@verbatim
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******************************************************************************
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* @file EEPROM/EEPROM_Emulation/readme.txt
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* @author MCD Application Team
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* @brief Description of the EEPROM_Emulation application.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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@endverbatim
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@par Application Description
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This application shows how to emulate EEPROM on internal flash.
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Please refer to AN3969 for futher details regarding this application.
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NUCLEO-F722ZE board LEDs can be used to monitor the application status:
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- LED2 is On when the application runs successfully.
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- LED2 is toggle in case of error.
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@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
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based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
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a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
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than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
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To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
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@note The application needs to ensure that the SysTick time base is always set to 1 millisecond
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to have correct HAL operation.
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@note Before using the application, ensure that dedicated sectors for EEPROM are erased
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to avoid a match with a valid page OPCODE.
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@par Keywords
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EEPROM, Emulation, Flash, Program, Erase, Sectors, OPCODE
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@Note If the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors,
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then it is highly recommended to enable the CPU cache and maintain its coherence at application level.
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The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes).
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@Note It is recommended to enable the cache and maintain its coherence, but depending on the use case
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It is also possible to configure the MPU as "Write through", to guarantee the write access coherence.
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In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable.
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Even though the user must manage the cache coherence for read accesses.
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Please refer to the AN4838 “Managing memory protection unit (MPU) in STM32 MCUs”
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Please refer to the AN4839 “Level 1 cache on STM32F7 Series”
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@par Directory contents
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- EEPROM/EEPROM_Emulation/Inc/stm32f7xx_hal_conf.h HAL Configuration file
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- EEPROM/EEPROM_Emulation/Inc/main.h Header for main.c module
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- EEPROM/EEPROM_Emulation/Inc/eeprom.h Header for eeprom.c module
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- EEPROM/EEPROM_Emulation/Inc/stm32f7xx_it.h Header for stm32f7xx_it.c
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- EEPROM/EEPROM_Emulation/Src/main.c Main program
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- EEPROM/EEPROM_Emulation/Src/eeprom.c EEPROM program
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- EEPROM/EEPROM_Emulation/Src/stm32f7xx_it.c Interrupt handlers
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- EEPROM/EEPROM_Emulation/Src/system_stm32f7xx.c STM32F7xx system clock configuration file
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@par Hardware and Software environment
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- This application runs on STM32F722ZE devices.
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- This application has been tested with NUCLEO-F722ZE board and can be
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easily tailored to any other supported device and development board.
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Table 1. EEPROM application implementation on NUCLEO-F722ZE
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/*** Platform ***|************* Implementation **************************|***** Configuration *****\
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****************************************************************************************************
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| Firmware | The EEPROM program is located at 0x08000000. The Flash| |
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| | routines (program/erase) are executed from the Flash | |
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| | memory. | |
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| | The size of this program is about 6 Kbytes and | |
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| | programmed on: | Sector 0 |
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| | ------------------------------------------------------|-------------------------|
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| | | |
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| | The flash zone used for the EEPROM emulation is | 32KB |
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| | located at 0x08008000 | (Sector2 - Sector3) |
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| | | |
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\**************************************************************************************************/
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@note
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Before using the application, ensure that dedicated sectors for EEPROM (FLASH_SECTOR_2 and FLASH_SECTOR_3)
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are erased to avoid a match with a valid page OPCODE.
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Following picture illustrates the situation in program memory:
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Top Flash Memory address /-------------------------------------------\ 0x0807FFFF
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| |
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| |
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| |
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| Sector 4 - Sector 7 |
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|-------------------------------------------| 0x08010000
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Sector 3 (16KB) | |
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| |
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| Flash used for EEPROM emulation mechanism | 0x0800C000
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Sector 2 (16KB) | |
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| |
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|-------------------------------------------| 0x08008000
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Sector 1 (16KB) | |
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| |
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|-------------------------------------------| 0x08004000
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| |
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Sector 0 (16KB) | flash used for implement the EEPROM |
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| emulation mechanism(6KB) |
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\-------------------------------------------/ 0x08000000
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@par How to use it ?
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In order to make the program work, you must do the following :
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- Open your preferred toolchain
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- Rebuild all files and load your image into target memory
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- Run the application
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*/
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