387 lines
12 KiB
C
387 lines
12 KiB
C
/**
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******************************************************************************
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* @file stm32f769i_eval_sram.c
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* @author MCD Application Team
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* @brief This file includes the SRAM driver for the IS61WV102416BLL-10M memory
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* device mounted on STM32F769I-EVAL evaluation boards.
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*
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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@verbatim
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How To use this driver:
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-----------------------
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- This driver is used to drive the IS61WV102416BLL-10M SRAM external memory mounted
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on STM32F769I-EVAL evaluation board.
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- This driver does not need a specific component driver for the SRAM device
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to be included with.
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Driver description:
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------------------
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+ Initialization steps:
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o Initialize the SRAM external memory using the BSP_SRAM_Init() function. This
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function includes the MSP layer hardware resources initialization and the
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FMC controller configuration to interface with the external SRAM memory.
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+ SRAM read/write operations
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o SRAM external memory can be accessed with read/write operations once it is
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initialized.
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Read/write operation can be performed with AHB access using the functions
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BSP_SRAM_ReadData()/BSP_SRAM_WriteData(), or by DMA transfer using the functions
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BSP_SRAM_ReadData_DMA()/BSP_SRAM_WriteData_DMA().
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o The AHB access is performed with 16-bit width transaction, the DMA transfer
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configuration is fixed at single (no burst) halfword transfer
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(see the SRAM_MspInit() static function).
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o User can implement his own functions for read/write access with his desired
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configurations.
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o If interrupt mode is used for DMA transfer, the function BSP_SRAM_DMA_IRQHandler()
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is called in IRQ handler file, to serve the generated interrupt once the DMA
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transfer is complete.
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@endverbatim
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******************************************************************************
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*/
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/* Dependencies
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- stm32f7xx_hal_sram.c
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- stm32f7xx_ll_fmc.c
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- stm32f7xx_hal_dma.c
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- stm32f7xx_hal_gpio.c
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- stm32f7xx_hal_cortex.c
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- stm32f7xx_hal_rcc_ex.h
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EndDependencies */
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f769i_eval_sram.h"
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/** @addtogroup BSP
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* @{
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*/
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/** @addtogroup STM32F769I_EVAL
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* @{
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*/
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/** @defgroup STM32F769I_EVAL_SRAM STM32F769I_EVAL SRAM
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* @{
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*/
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/** @defgroup STM32F769I_EVAL_SRAM_Private_Types_Definitions SRAM Private Types Definitions
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup STM32F769I_EVAL_SRAM_Private_Defines EVAL SRAM Private Defines
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup STM32F769I_EVAL_SRAM_Private_Macros SRAM Private Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup STM32F769I_EVAL_SRAM_Private_Variables SRAM Private Variables
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* @{
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*/
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SRAM_HandleTypeDef sramHandle;
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static FMC_NORSRAM_TimingTypeDef Timing;
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/**
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* @}
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*/
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/** @defgroup STM32F769I_EVAL_SRAM_Private_Functions_Prototypes SRAM Private Functions Prototypes
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup STM32F769I_EVAL_SRAM_Private_Functions SRAM Private Functions
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* @{
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*/
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/**
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* @brief Initializes the SRAM device.
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* @retval SRAM status
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*/
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uint8_t BSP_SRAM_Init(void)
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{
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static uint8_t sram_status = SRAM_ERROR;
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/* SRAM device configuration */
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sramHandle.Instance = FMC_NORSRAM_DEVICE;
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sramHandle.Extended = FMC_NORSRAM_EXTENDED_DEVICE;
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/* SRAM device configuration */
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/* Timing configuration derived from system clock (up to 216Mhz)
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for 108Mhz as SRAM clock frequency */
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Timing.AddressSetupTime = 2;
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Timing.AddressHoldTime = 1;
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Timing.DataSetupTime = 2;
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Timing.BusTurnAroundDuration = 1;
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Timing.CLKDivision = 2;
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Timing.DataLatency = 2;
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Timing.AccessMode = FMC_ACCESS_MODE_A;
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sramHandle.Init.NSBank = FMC_NORSRAM_BANK3;
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sramHandle.Init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE;
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sramHandle.Init.MemoryType = FMC_MEMORY_TYPE_SRAM;
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sramHandle.Init.MemoryDataWidth = SRAM_MEMORY_WIDTH;
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sramHandle.Init.BurstAccessMode = SRAM_BURSTACCESS;
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sramHandle.Init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW;
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sramHandle.Init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS;
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sramHandle.Init.WriteOperation = FMC_WRITE_OPERATION_ENABLE;
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sramHandle.Init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE;
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sramHandle.Init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE;
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sramHandle.Init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE;
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sramHandle.Init.WriteBurst = SRAM_WRITEBURST;
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sramHandle.Init.ContinuousClock = CONTINUOUSCLOCK_FEATURE;
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/* SRAM controller initialization */
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BSP_SRAM_MspInit(&sramHandle, NULL); /* __weak function can be rewritten by the application */
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if(HAL_SRAM_Init(&sramHandle, &Timing, &Timing) != HAL_OK)
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{
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sram_status = SRAM_ERROR;
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}
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else
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{
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sram_status = SRAM_OK;
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}
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return sram_status;
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}
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/**
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* @brief DeInitializes the SRAM device.
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* @retval SRAM status
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*/
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uint8_t BSP_SRAM_DeInit(void)
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{
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static uint8_t sram_status = SRAM_ERROR;
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/* SRAM device de-initialization */
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sramHandle.Instance = FMC_NORSRAM_DEVICE;
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sramHandle.Extended = FMC_NORSRAM_EXTENDED_DEVICE;
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if(HAL_SRAM_DeInit(&sramHandle) != HAL_OK)
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{
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sram_status = SRAM_ERROR;
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}
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else
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{
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sram_status = SRAM_OK;
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}
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/* SRAM controller de-initialization */
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BSP_SRAM_MspDeInit(&sramHandle, NULL);
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return sram_status;
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}
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/**
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* @brief Reads an amount of data from the SRAM device in polling mode.
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* @param uwStartAddress: Read start address
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* @param pData: Pointer to data to be read
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* @param uwDataSize: Size of read data from the memory
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* @retval SRAM status
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*/
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uint8_t BSP_SRAM_ReadData(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize)
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{
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if(HAL_SRAM_Read_16b(&sramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
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{
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return SRAM_ERROR;
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}
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else
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{
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return SRAM_OK;
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}
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}
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/**
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* @brief Reads an amount of data from the SRAM device in DMA mode.
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* @param uwStartAddress: Read start address
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* @param pData: Pointer to data to be read
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* @param uwDataSize: Size of read data from the memory
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* @retval SRAM status
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*/
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uint8_t BSP_SRAM_ReadData_DMA(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize)
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{
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if(HAL_SRAM_Read_DMA(&sramHandle, (uint32_t *)uwStartAddress, (uint32_t *)pData, uwDataSize) != HAL_OK)
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{
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return SRAM_ERROR;
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}
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else
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{
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return SRAM_OK;
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}
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}
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/**
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* @brief Writes an amount of data from the SRAM device in polling mode.
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* @param uwStartAddress: Write start address
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* @param pData: Pointer to data to be written
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* @param uwDataSize: Size of written data from the memory
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* @retval SRAM status
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*/
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uint8_t BSP_SRAM_WriteData(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize)
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{
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if(HAL_SRAM_Write_16b(&sramHandle, (uint32_t *)uwStartAddress, pData, uwDataSize) != HAL_OK)
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{
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return SRAM_ERROR;
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}
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else
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{
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return SRAM_OK;
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}
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}
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/**
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* @brief Writes an amount of data from the SRAM device in DMA mode.
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* @param uwStartAddress: Write start address
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* @param pData: Pointer to data to be written
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* @param uwDataSize: Size of written data from the memory
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* @retval SRAM status
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*/
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uint8_t BSP_SRAM_WriteData_DMA(uint32_t uwStartAddress, uint16_t *pData, uint32_t uwDataSize)
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{
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if(HAL_SRAM_Write_DMA(&sramHandle, (uint32_t *)uwStartAddress, (uint32_t *)pData, uwDataSize) != HAL_OK)
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{
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return SRAM_ERROR;
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}
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else
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{
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return SRAM_OK;
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}
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}
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/**
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* @brief Initializes SRAM MSP.
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* @param hsram: SRAM handle
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* @param Params
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* @retval None
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*/
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__weak void BSP_SRAM_MspInit(SRAM_HandleTypeDef *hsram, void *Params)
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{
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static DMA_HandleTypeDef dma_handle;
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GPIO_InitTypeDef gpio_init_structure;
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/* Enable FMC clock */
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__HAL_RCC_FMC_CLK_ENABLE();
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/* Enable chosen DMAx clock */
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__SRAM_DMAx_CLK_ENABLE();
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/* Enable GPIOs clock */
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__HAL_RCC_GPIOD_CLK_ENABLE();
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__HAL_RCC_GPIOE_CLK_ENABLE();
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__HAL_RCC_GPIOF_CLK_ENABLE();
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__HAL_RCC_GPIOG_CLK_ENABLE();
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/* Common GPIO configuration */
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gpio_init_structure.Mode = GPIO_MODE_AF_PP;
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gpio_init_structure.Pull = GPIO_PULLUP;
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gpio_init_structure.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
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gpio_init_structure.Alternate = GPIO_AF12_FMC;
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/* GPIOD configuration */
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gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_8 |\
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GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13 |\
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GPIO_PIN_14 | GPIO_PIN_15;
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HAL_GPIO_Init(GPIOD, &gpio_init_structure);
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/* GPIOE configuration */
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gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3| GPIO_PIN_4 | GPIO_PIN_7 |\
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GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 |\
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GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
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HAL_GPIO_Init(GPIOE, &gpio_init_structure);
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/* GPIOF configuration */
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gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
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GPIO_PIN_5 | GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15;
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HAL_GPIO_Init(GPIOF, &gpio_init_structure);
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/* GPIOG configuration */
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gpio_init_structure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2| GPIO_PIN_3 | GPIO_PIN_4 |\
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GPIO_PIN_5 | GPIO_PIN_6;
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HAL_GPIO_Init(GPIOG, &gpio_init_structure);
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/* Configure common DMA parameters */
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dma_handle.Init.Channel = SRAM_DMAx_CHANNEL;
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dma_handle.Init.Direction = DMA_MEMORY_TO_MEMORY;
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dma_handle.Init.PeriphInc = DMA_PINC_ENABLE;
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dma_handle.Init.MemInc = DMA_MINC_ENABLE;
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dma_handle.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
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dma_handle.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
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dma_handle.Init.Mode = DMA_NORMAL;
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dma_handle.Init.Priority = DMA_PRIORITY_HIGH;
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dma_handle.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
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dma_handle.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
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dma_handle.Init.MemBurst = DMA_MBURST_SINGLE;
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dma_handle.Init.PeriphBurst = DMA_PBURST_SINGLE;
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dma_handle.Instance = SRAM_DMAx_STREAM;
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/* Associate the DMA handle */
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__HAL_LINKDMA(hsram, hdma, dma_handle);
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/* Deinitialize the Stream for new transfer */
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HAL_DMA_DeInit(&dma_handle);
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/* Configure the DMA Stream */
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HAL_DMA_Init(&dma_handle);
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/* NVIC configuration for DMA transfer complete interrupt */
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HAL_NVIC_SetPriority(SRAM_DMAx_IRQn, 0x0F, 0);
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HAL_NVIC_EnableIRQ(SRAM_DMAx_IRQn);
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}
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/**
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* @brief DeInitializes SRAM MSP.
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* @param hsram: SRAM handle
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* @param Params
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* @retval None
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*/
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__weak void BSP_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram, void *Params)
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{
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static DMA_HandleTypeDef dma_handle;
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/* Disable NVIC configuration for DMA interrupt */
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HAL_NVIC_DisableIRQ(SRAM_DMAx_IRQn);
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/* Deinitialize the stream for new transfer */
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dma_handle.Instance = SRAM_DMAx_STREAM;
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HAL_DMA_DeInit(&dma_handle);
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/* GPIO pins clock, FMC clock and DMA clock can be shut down in the applications
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by surcharging this __weak function */
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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