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/**
@page IWDG_RefreshUntilUserEvent IWDG example
@verbatim
******************************************************************************
* @file Examples_LL/IWDG/IWDG_RefreshUntilUserEvent/readme.txt
* @author MCD Application Team
* @brief Description of the IWDG_RefreshUntilUserEvent example.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@endverbatim
@par Example Description
How to configure the IWDG to ensure period counter update and
generate an MCU IWDG reset when a user button is pressed. The peripheral
is initialized with LL unitary service functions to optimize
for performance and size.
Example Configuration:
Configure the IWDG (prescaler, counter) and enable it.
Infinite refresh of the IWDG down-counter done in the main loop.
LED1 is blinking fast & continuously
Example Execution:
When User Button is pressed, the down-counter automatic refresh mechanism is
disable and thus, reset will occur. After a reset, when re-entering in the main,
RCC IWDG Reset Flag will be checked and if we are back from a IWDG reset the LED1
will be switch ON.
Waiting a new user button pressed to re-activate the IWDG
@par Keywords
System, IWDG, Timeout, MCU Reset, Downcounter, Timer, Measure Frequency
@NoteIf the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors,
then it is highly recommended to enable the CPU cache and maintain its coherence at application level.
The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes).
@Note It is recommended to enable the cache and maintain its coherence, but depending on the use case
It is also possible to configure the MPU as "Write through", to guarantee the write access coherence.
In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable.
Even though the user must manage the cache coherence for read accesses.
Please refer to the AN4838 “Managing memory protection unit (MPU) in STM32 MCUs”
Please refer to the AN4839 “Level 1 cache on STM32F7 Series”
@par Directory contents
- IWDG/IWDG_RefreshUntilUserEvent/Inc/stm32f7xx_it.h Interrupt handlers header file
- IWDG/IWDG_RefreshUntilUserEvent/Inc/main.h Header for main.c module
- IWDG/IWDG_RefreshUntilUserEvent/Inc/stm32_assert.h Template file to include assert_failed function
- IWDG/IWDG_RefreshUntilUserEvent/Src/stm32f7xx_it.c Interrupt handlers
- IWDG/IWDG_RefreshUntilUserEvent/Src/main.c Main program
- IWDG/IWDG_RefreshUntilUserEvent/Src/system_stm32f7xx.c STM32F7xx system source file
@par Hardware and Software environment
- This example runs on STM32F767xx devices.
- This example has been tested with NUCLEO-F767ZI board and can be
easily tailored to any other supported device and development board.
@par How to use it ?
In order to make the program work, you must do the following :
- Open your preferred toolchain
- Rebuild all files and load your image into target memory
- Run the example
*/
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