649 lines
21 KiB
C
649 lines
21 KiB
C
/**
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******************************************************************************
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* @file system_stm32f7xx.c
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* @author MCD Application Team
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* @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
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*
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* This file provides two functions and one global variable to be called from
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* user application:
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* - SystemInit(): This function is called at startup just after reset and
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* before branch to main program. This call is made inside
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* the "startup_stm32f7xx.s" file.
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*
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* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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* by the user application to setup the SysTick
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* timer or configure other parameters.
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*
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* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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* be called whenever the core clock is changed
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* during program execution.
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*
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*
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32f7xx_system
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* @{
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*/
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/** @addtogroup STM32F7xx_System_Private_Includes
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* @{
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*/
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#include "stm32f7xx.h"
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#if !defined (HSE_VALUE)
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#define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
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#endif /* HSE_VALUE */
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#if !defined (HSI_VALUE)
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#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
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#endif /* HSI_VALUE */
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/**
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* @}
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*/
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/** @addtogroup STM32F7xx_System_Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32F7xx_System_Private_Defines
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* @{
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*/
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/************************* Miscellaneous Configuration ************************/
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/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
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on STMicroelectronics EVAL/Discovery boards as data memory */
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/*!< In case of EVAL/Discovery’s LCD use in application code, the DATA_IN_ExtSDRAM define
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need to be added in the project preprocessor to avoid SDRAM multiple configuration
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(the LCD uses SDRAM as frame buffer, and its configuration is done by the BSP_SDRAM_Init()) */
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/* #define DATA_IN_ExtSRAM */
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/* #define DATA_IN_ExtSDRAM */
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/*!< Uncomment the following line if you need to relocate your vector Table in
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Internal SRAM. */
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/* #define VECT_TAB_SRAM */
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#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
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This value must be a multiple of 0x200. */
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/******************************************************************************/
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/**
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* @}
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*/
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/** @addtogroup STM32F7xx_System_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32F7xx_System_Private_Variables
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* @{
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*/
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/* This variable is updated in three ways:
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1) by calling CMSIS function SystemCoreClockUpdate()
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2) by calling HAL API function HAL_RCC_GetHCLKFreq()
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3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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Note: If you use this function to configure the system clock; then there
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is no need to call the 2 first functions listed above, since SystemCoreClock
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variable is updated automatically.
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*/
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uint32_t SystemCoreClock = 16000000;
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const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
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/**
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* @}
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*/
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/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes
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* @{
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*/
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#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
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static void SystemInit_ExtMemCtl(void);
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#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
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/**
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* @}
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*/
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/** @addtogroup STM32F7xx_System_Private_Functions
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* @{
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*/
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/**
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* @brief Setup the microcontroller system
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* Initialize the Embedded Flash Interface, the PLL and update the
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* SystemFrequency variable.
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* @param None
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* @retval None
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*/
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void SystemInit(void)
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{
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/* FPU settings ------------------------------------------------------------*/
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
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#endif
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/* Reset the RCC clock configuration to the default reset state ------------*/
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/* Set HSION bit */
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RCC->CR |= (uint32_t)0x00000001;
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/* Reset CFGR register */
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RCC->CFGR = 0x00000000;
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/* Reset HSEON, CSSON and PLLON bits */
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RCC->CR &= (uint32_t)0xFEF6FFFF;
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/* Reset PLLCFGR register */
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RCC->PLLCFGR = 0x24003010;
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/* Reset HSEBYP bit */
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RCC->CR &= (uint32_t)0xFFFBFFFF;
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/* Disable all interrupts */
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RCC->CIR = 0x00000000;
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#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
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SystemInit_ExtMemCtl();
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#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
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/* Configure the Vector Table location add offset address ------------------*/
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#ifdef VECT_TAB_SRAM
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SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
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#else
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SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
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#endif
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}
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/**
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* @brief Update SystemCoreClock variable according to Clock Register Values.
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* The SystemCoreClock variable contains the core clock (HCLK), it can
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* be used by the user application to setup the SysTick timer or configure
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* other parameters.
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*
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* @note Each time the core clock (HCLK) changes, this function must be called
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* to update SystemCoreClock variable value. Otherwise, any configuration
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* based on this variable will be incorrect.
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*
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* @note - The system frequency computed by this function is not the real
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* frequency in the chip. It is calculated based on the predefined
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* constant and the selected clock source:
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*
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* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
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*
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* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
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*
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* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
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* or HSI_VALUE(*) multiplied/divided by the PLL factors.
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*
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* (*) HSI_VALUE is a constant defined in stm32f7xx.h file (default value
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* 16 MHz) but the real value may vary depending on the variations
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* in voltage and temperature.
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*
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* (**) HSE_VALUE is a constant defined in stm32f7xx.h file (default value
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* 25 MHz), user has to ensure that HSE_VALUE is same as the real
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* frequency of the crystal used. Otherwise, this function may
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* have wrong result.
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*
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* - The result of this function could be not correct when using fractional
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* value for HSE crystal.
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*
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* @param None
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* @retval None
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*/
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void SystemCoreClockUpdate(void)
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{
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uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
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/* Get SYSCLK source -------------------------------------------------------*/
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tmp = RCC->CFGR & RCC_CFGR_SWS;
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switch (tmp)
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{
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case 0x00: /* HSI used as system clock source */
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SystemCoreClock = HSI_VALUE;
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break;
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case 0x04: /* HSE used as system clock source */
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SystemCoreClock = HSE_VALUE;
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break;
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case 0x08: /* PLL used as system clock source */
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/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
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SYSCLK = PLL_VCO / PLL_P
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*/
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pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
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pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
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if (pllsource != 0)
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{
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/* HSE used as PLL clock source */
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pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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}
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else
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{
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/* HSI used as PLL clock source */
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pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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}
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pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
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SystemCoreClock = pllvco/pllp;
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break;
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default:
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SystemCoreClock = HSI_VALUE;
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break;
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}
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/* Compute HCLK frequency --------------------------------------------------*/
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/* Get HCLK prescaler */
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tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
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/* HCLK frequency */
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SystemCoreClock >>= tmp;
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}
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#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
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/**
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* @brief Setup the external memory controller.
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* Called in startup_stm32f7xx.s before jump to main.
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* This function configures the external memories (SRAM/SDRAM)
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* This SRAM/SDRAM will be used as program data memory (including heap and stack).
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* @param None
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* @retval None
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*/
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void SystemInit_ExtMemCtl(void)
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{
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__IO uint32_t tmp = 0;
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#if defined (DATA_IN_ExtSDRAM) && defined (DATA_IN_ExtSRAM)
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register uint32_t tmpreg = 0, timeout = 0xFFFF;
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register uint32_t index;
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/* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
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clock */
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RCC->AHB1ENR |= 0x000001F8;
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/* Delay after an RCC peripheral clock enabling */
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tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
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/* Connect PDx pins to FMC Alternate function */
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GPIOD->AFR[0] = 0x00CC00CC;
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GPIOD->AFR[1] = 0xCCCCCCCC;
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/* Configure PDx pins in Alternate function mode */
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GPIOD->MODER = 0xAAAA0A0A;
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/* Configure PDx pins speed to 100 MHz */
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GPIOD->OSPEEDR = 0xFFFF0F0F;
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/* Configure PDx pins Output type to push-pull */
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GPIOD->OTYPER = 0x00000000;
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/* No pull-up, pull-down for PDx pins */
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GPIOD->PUPDR = 0x55550505;
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/* Connect PEx pins to FMC Alternate function */
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GPIOE->AFR[0] = 0xC00CC0CC;
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GPIOE->AFR[1] = 0xCCCCCCCC;
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/* Configure PEx pins in Alternate function mode */
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GPIOE->MODER = 0xAAAA828A;
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/* Configure PEx pins speed to 100 MHz */
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GPIOE->OSPEEDR = 0xFFFFC3CF;
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/* Configure PEx pins Output type to push-pull */
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GPIOE->OTYPER = 0x00000000;
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/* No pull-up, pull-down for PEx pins */
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GPIOE->PUPDR = 0x55554145;
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/* Connect PFx pins to FMC Alternate function */
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GPIOF->AFR[0] = 0x00CCCCCC;
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GPIOF->AFR[1] = 0xCCCCC000;
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/* Configure PFx pins in Alternate function mode */
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GPIOF->MODER = 0xAA800AAA;
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/* Configure PFx pins speed to 100 MHz */
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GPIOF->OSPEEDR = 0xFFC00FFF;
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/* Configure PFx pins Output type to push-pull */
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GPIOF->OTYPER = 0x00000000;
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/* No pull-up, pull-down for PFx pins */
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GPIOF->PUPDR = 0x55400555;
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/* Connect PGx pins to FMC Alternate function */
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GPIOG->AFR[0] = 0x0CCCCCCC;
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GPIOG->AFR[1] = 0xC000000C;
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/* Configure PGx pins in Alternate function mode */
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GPIOG->MODER = 0x80022AAA;
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/* Configure PGx pins speed to 100 MHz */
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GPIOG->OSPEEDR = 0xC0033FFF;
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/* Configure PGx pins Output type to push-pull */
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GPIOG->OTYPER = 0x00000000;
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/* No pull-up, pull-down for PGx pins */
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GPIOG->PUPDR = 0x40011555;
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/* Connect PHx pins to FMC Alternate function */
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GPIOH->AFR[0] = 0x00C0CC00;
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GPIOH->AFR[1] = 0xCCCCCCCC;
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/* Configure PHx pins in Alternate function mode */
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GPIOH->MODER = 0xAAAA08A0;
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/* Configure PHx pins speed to 100 MHz */
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GPIOH->OSPEEDR = 0xFFFF0CF0;
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/* Configure PHx pins Output type to push-pull */
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GPIOH->OTYPER = 0x00000000;
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/* No pull-up, pull-down for PHx pins */
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GPIOH->PUPDR = 0x55550450;
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/* Connect PIx pins to FMC Alternate function */
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GPIOI->AFR[0] = 0xCCCCCCCC;
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GPIOI->AFR[1] = 0x00000CC0;
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/* Configure PIx pins in Alternate function mode */
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GPIOI->MODER = 0x0028AAAA;
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/* Configure PIx pins speed to 100 MHz */
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GPIOI->OSPEEDR = 0x003CFFFF;
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/* Configure PIx pins Output type to push-pull */
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GPIOI->OTYPER = 0x00000000;
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/* No pull-up, pull-down for PIx pins */
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GPIOI->PUPDR = 0x00145555;
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/*-- FMC Configuration ------------------------------------------------------*/
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/* Enable the FMC interface clock */
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RCC->AHB3ENR |= 0x00000001;
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/* Delay after an RCC peripheral clock enabling */
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tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
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/* Configure and enable Bank1_SRAM2 */
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FMC_Bank1->BTCR[4] = 0x00001091;
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FMC_Bank1->BTCR[5] = 0x00110212;
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FMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
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/* Configure and enable SDRAM bank1 */
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FMC_Bank5_6->SDCR[0] = 0x000019E5;
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FMC_Bank5_6->SDTR[0] = 0x01116361;
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/* SDRAM initialization sequence */
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/* Clock enable command */
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FMC_Bank5_6->SDCMR = 0x00000011;
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tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
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while((tmpreg != 0) && (timeout-- > 0))
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{
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tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
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}
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/* Delay */
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for (index = 0; index<1000; index++);
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/* PALL command */
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FMC_Bank5_6->SDCMR = 0x00000012;
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timeout = 0xFFFF;
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while((tmpreg != 0) && (timeout-- > 0))
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{
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tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
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}
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/* Auto refresh command */
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FMC_Bank5_6->SDCMR = 0x000000F3;
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timeout = 0xFFFF;
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while((tmpreg != 0) && (timeout-- > 0))
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{
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tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
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}
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/* MRD register program */
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FMC_Bank5_6->SDCMR = 0x00046014;
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timeout = 0xFFFF;
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while((tmpreg != 0) && (timeout-- > 0))
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{
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tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
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}
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/* Set refresh count */
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tmpreg = FMC_Bank5_6->SDRTR;
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FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));
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/* Disable write protection */
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tmpreg = FMC_Bank5_6->SDCR[0];
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FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
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#elif defined (DATA_IN_ExtSDRAM)
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register uint32_t tmpreg = 0, timeout = 0xFFFF;
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register uint32_t index;
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/* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
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clock */
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RCC->AHB1ENR |= 0x000001F8;
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/* Delay after an RCC peripheral clock enabling */
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tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
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/* Connect PDx pins to FMC Alternate function */
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GPIOD->AFR[0] = 0x000000CC;
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GPIOD->AFR[1] = 0xCC000CCC;
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/* Configure PDx pins in Alternate function mode */
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GPIOD->MODER = 0xA02A000A;
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/* Configure PDx pins speed to 100 MHz */
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GPIOD->OSPEEDR = 0xF03F000F;
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/* Configure PDx pins Output type to push-pull */
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GPIOD->OTYPER = 0x00000000;
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/* No pull-up, pull-down for PDx pins */
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GPIOD->PUPDR = 0x50150005;
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/* Connect PEx pins to FMC Alternate function */
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GPIOE->AFR[0] = 0xC00000CC;
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GPIOE->AFR[1] = 0xCCCCCCCC;
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/* Configure PEx pins in Alternate function mode */
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GPIOE->MODER = 0xAAAA800A;
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/* Configure PEx pins speed to 100 MHz */
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GPIOE->OSPEEDR = 0xFFFFC00F;
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/* Configure PEx pins Output type to push-pull */
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GPIOE->OTYPER = 0x00000000;
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/* No pull-up, pull-down for PEx pins */
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GPIOE->PUPDR = 0x55554005;
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/* Connect PFx pins to FMC Alternate function */
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GPIOF->AFR[0] = 0x00CCCCCC;
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GPIOF->AFR[1] = 0xCCCCC000;
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/* Configure PFx pins in Alternate function mode */
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GPIOF->MODER = 0xAA800AAA;
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/* Configure PFx pins speed to 100 MHz */
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GPIOF->OSPEEDR = 0xFFC00FFF;
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/* Configure PFx pins Output type to push-pull */
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GPIOF->OTYPER = 0x00000000;
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/* No pull-up, pull-down for PFx pins */
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GPIOF->PUPDR = 0x55400555;
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/* Connect PGx pins to FMC Alternate function */
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GPIOG->AFR[0] = 0x00CC00CC;
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GPIOG->AFR[1] = 0xC000000C;
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/* Configure PGx pins in Alternate function mode */
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GPIOG->MODER = 0x80020A0A;
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/* Configure PGx pins speed to 100 MHz */
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GPIOG->OSPEEDR = 0xC0030F0F;
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/* Configure PGx pins Output type to push-pull */
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GPIOG->OTYPER = 0x00000000;
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/* No pull-up, pull-down for PGx pins */
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GPIOG->PUPDR = 0x40010505;
|
||
|
||
/* Connect PHx pins to FMC Alternate function */
|
||
GPIOH->AFR[0] = 0x00C0CC00;
|
||
GPIOH->AFR[1] = 0xCCCCCCCC;
|
||
/* Configure PHx pins in Alternate function mode */
|
||
GPIOH->MODER = 0xAAAA08A0;
|
||
/* Configure PHx pins speed to 100 MHz */
|
||
GPIOH->OSPEEDR = 0xFFFF0CF0;
|
||
/* Configure PHx pins Output type to push-pull */
|
||
GPIOH->OTYPER = 0x00000000;
|
||
/* No pull-up, pull-down for PHx pins */
|
||
GPIOH->PUPDR = 0x55550450;
|
||
|
||
/* Connect PIx pins to FMC Alternate function */
|
||
GPIOI->AFR[0] = 0xCCCCCCCC;
|
||
GPIOI->AFR[1] = 0x00000CC0;
|
||
/* Configure PIx pins in Alternate function mode */
|
||
GPIOI->MODER = 0x0028AAAA;
|
||
/* Configure PIx pins speed to 100 MHz */
|
||
GPIOI->OSPEEDR = 0x003CFFFF;
|
||
/* Configure PIx pins Output type to push-pull */
|
||
GPIOI->OTYPER = 0x00000000;
|
||
/* No pull-up, pull-down for PIx pins */
|
||
GPIOI->PUPDR = 0x00145555;
|
||
|
||
/*-- FMC Configuration ------------------------------------------------------*/
|
||
/* Enable the FMC interface clock */
|
||
RCC->AHB3ENR |= 0x00000001;
|
||
|
||
/* Delay after an RCC peripheral clock enabling */
|
||
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
|
||
|
||
/* Configure and enable SDRAM bank1 */
|
||
FMC_Bank5_6->SDCR[0] = 0x000019E5;
|
||
FMC_Bank5_6->SDTR[0] = 0x01116361;
|
||
|
||
/* SDRAM initialization sequence */
|
||
/* Clock enable command */
|
||
FMC_Bank5_6->SDCMR = 0x00000011;
|
||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||
while((tmpreg != 0) && (timeout-- > 0))
|
||
{
|
||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||
}
|
||
|
||
/* Delay */
|
||
for (index = 0; index<1000; index++);
|
||
|
||
/* PALL command */
|
||
FMC_Bank5_6->SDCMR = 0x00000012;
|
||
timeout = 0xFFFF;
|
||
while((tmpreg != 0) && (timeout-- > 0))
|
||
{
|
||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||
}
|
||
|
||
/* Auto refresh command */
|
||
FMC_Bank5_6->SDCMR = 0x000000F3;
|
||
timeout = 0xFFFF;
|
||
while((tmpreg != 0) && (timeout-- > 0))
|
||
{
|
||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||
}
|
||
|
||
/* MRD register program */
|
||
FMC_Bank5_6->SDCMR = 0x00046014;
|
||
timeout = 0xFFFF;
|
||
while((tmpreg != 0) && (timeout-- > 0))
|
||
{
|
||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||
}
|
||
|
||
/* Set refresh count */
|
||
tmpreg = FMC_Bank5_6->SDRTR;
|
||
FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));
|
||
|
||
/* Disable write protection */
|
||
tmpreg = FMC_Bank5_6->SDCR[0];
|
||
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
|
||
|
||
#elif defined(DATA_IN_ExtSRAM)
|
||
/*-- GPIOs Configuration -----------------------------------------------------*/
|
||
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
|
||
RCC->AHB1ENR |= 0x00000078;
|
||
|
||
/* Delay after an RCC peripheral clock enabling */
|
||
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);
|
||
|
||
/* Connect PDx pins to FMC Alternate function */
|
||
GPIOD->AFR[0] = 0x00CC00CC;
|
||
GPIOD->AFR[1] = 0xCCCCCCCC;
|
||
/* Configure PDx pins in Alternate function mode */
|
||
GPIOD->MODER = 0xAAAA0A0A;
|
||
/* Configure PDx pins speed to 100 MHz */
|
||
GPIOD->OSPEEDR = 0xFFFF0F0F;
|
||
/* Configure PDx pins Output type to push-pull */
|
||
GPIOD->OTYPER = 0x00000000;
|
||
/* No pull-up, pull-down for PDx pins */
|
||
GPIOD->PUPDR = 0x55550505;
|
||
|
||
/* Connect PEx pins to FMC Alternate function */
|
||
GPIOE->AFR[0] = 0xC00CC0CC;
|
||
GPIOE->AFR[1] = 0xCCCCCCCC;
|
||
/* Configure PEx pins in Alternate function mode */
|
||
GPIOE->MODER = 0xAAAA828A;
|
||
/* Configure PEx pins speed to 100 MHz */
|
||
GPIOE->OSPEEDR = 0xFFFFC3CF;
|
||
/* Configure PEx pins Output type to push-pull */
|
||
GPIOE->OTYPER = 0x00000000;
|
||
/* No pull-up, pull-down for PEx pins */
|
||
GPIOE->PUPDR = 0x55554145;
|
||
|
||
/* Connect PFx pins to FMC Alternate function */
|
||
GPIOF->AFR[0] = 0x00CCCCCC;
|
||
GPIOF->AFR[1] = 0xCCCC0000;
|
||
/* Configure PFx pins in Alternate function mode */
|
||
GPIOF->MODER = 0xAA000AAA;
|
||
/* Configure PFx pins speed to 100 MHz */
|
||
GPIOF->OSPEEDR = 0xFF000FFF;
|
||
/* Configure PFx pins Output type to push-pull */
|
||
GPIOF->OTYPER = 0x00000000;
|
||
/* No pull-up, pull-down for PFx pins */
|
||
GPIOF->PUPDR = 0x55000555;
|
||
|
||
/* Connect PGx pins to FMC Alternate function */
|
||
GPIOG->AFR[0] = 0x0CCCCCCC;
|
||
GPIOG->AFR[1] = 0x00000000;
|
||
/* Configure PGx pins in Alternate function mode */
|
||
GPIOG->MODER = 0x00002AAA;
|
||
/* Configure PGx pins speed to 100 MHz */
|
||
GPIOG->OSPEEDR = 0x00003FFF;
|
||
/* Configure PGx pins Output type to push-pull */
|
||
GPIOG->OTYPER = 0x00000000;
|
||
/* No pull-up, pull-down for PGx pins */
|
||
GPIOG->PUPDR = 0x00001555;
|
||
|
||
/*-- FMC/FSMC Configuration --------------------------------------------------*/
|
||
/* Enable the FMC/FSMC interface clock */
|
||
RCC->AHB3ENR |= 0x00000001;
|
||
|
||
/* Delay after an RCC peripheral clock enabling */
|
||
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
|
||
|
||
/* Configure and enable Bank1_SRAM3 */
|
||
FMC_Bank1->BTCR[4] = 0x00001091;
|
||
FMC_Bank1->BTCR[5] = 0x00110212;
|
||
FMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
|
||
|
||
#endif /* DATA_IN_ExtSRAM */
|
||
|
||
/*
|
||
* Disable the FMC bank1 (enabled after reset).
|
||
* This, prevents CPU speculation access on this bank which blocks the use of FMC during
|
||
* 24us. During this time the others FMC master (such as LTDC) cannot use it!
|
||
*/
|
||
FMC_Bank1->BTCR[0] = 0x000030d2;
|
||
|
||
(void)(tmp);
|
||
}
|
||
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
|
||
|
||
/**
|
||
* @}
|
||
*/
|
||
|
||
/**
|
||
* @}
|
||
*/
|
||
|
||
/**
|
||
* @}
|
||
*/
|