/**
@page TIM_ExtTriggerSynchro TIM External Trigger Synchro example
@verbatim
******************************************************************************
* @file TIM/TIM_ExtTriggerSynchro/readme.txt
* @author MCD Application Team
* @brief Description of the TIM External Trigger Synchro example.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@endverbatim
@par Example Description
Synchronization of TIM peripherals in Cascade mode with an external trigger.
Three timers are used in this example:
1/TIM1 is configured as Master Timer:
- Toggle Mode is used
- The TIM1 Enable event is used as Trigger Output
2/TIM1 is configured as Slave Timer for an external Trigger connected to TIM1
TI2 pin (TIM1 CH2 configured as input pin):
- The TIM1 TI2FP2 is used as Trigger Input
- Rising edge is used to start and stop the TIM1: Gated Mode.
3/TIM4 is slave for TIM1 and Master for TIM5,
- Toggle Mode is used
- The ITR0 (TIM1) is used as input trigger
- Gated mode is used, so start and stop of slave counter
are controlled by the Master trigger output signal(TIM1 enable event).
- The TIM4 enable event is used as Trigger Output.
4/TIM5 is slave for TIM4,
- Toggle Mode is used
- The ITR2 (TIM4) is used as input trigger
- Gated mode is used, so start and stop of slave counter
are controlled by the Master trigger output signal(TIM4 enable event).
The TIM1CLK is set to SystemCoreClock,
TIM4CLK is set to (SystemCoreClock/2) and
TIM5CLK frequency is set to (SystemCoreClock/2),
to get TIMx counter clock at 20 MHz the Prescaler is computed as following:
- Prescaler = (TIMx CLK / TIMx counter clock) - 1
SystemCoreClock is set to 216 MHz.
TIMx frequency = TIMx counter clock/ 2*(TIMx_Period + 1) = 100 KHz.
The starts and stops of the TIM1 counters are controlled by the external trigger.
The TIM4 starts and stops are controlled by the TIM1, and the TIM5 starts and
stops are controlled by the TIM4.
@note Care must be taken when using HAL_Delay(), this function provides accurate
delay (in milliseconds) based on variable incremented in SysTick ISR. This
implies that if HAL_Delay() is called from a peripheral ISR process, then
the SysTick interrupt must have higher priority (numerically lower)
than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
@note The application need to ensure that the SysTick time base is always set to 1 millisecond
to have correct HAL operation.
@par Keywords
Timers, PWM, External Trigger, Synchronization, Cascade mode, Master, Slave, Duty Cycle, Waveform,
Oscilloscope, Output, Signal,
@Note<74>If the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors,
<20><><A0><A0><A0>then it is highly recommended to enable the CPU cache and maintain its coherence at application level.
<0A><><A0><A0><A0><A0>The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes).
@Note It is recommended to enable the cache and maintain its coherence, but depending on the use case
<0A><><A0><A0><A0> It is also possible to configure the MPU as "Write through", to guarantee the write access coherence.
<0A><><A0><A0><A0><A0>In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable.
<0A><><A0><A0><A0><A0>Even though the user must manage the cache coherence for read accesses.
<0A><><A0><A0><A0><A0>Please refer to the AN4838 <20>Managing memory protection unit (MPU) in STM32 MCUs<55>
<0A><><A0><A0><A0><A0>Please refer to the AN4839 <20>Level 1 cache on STM32F7 Series<65>
@par Directory contents
- TIM/TIM_ExtTriggerSynchro/Inc/stm32f7xx_hal_conf.h HAL configuration file
- TIM/TIM_ExtTriggerSynchro/Inc/stm32f7xx_it.h Interrupt handlers header file
- TIM/TIM_ExtTriggerSynchro/Inc/main.h Header for main.c module
- TIM/TIM_ExtTriggerSynchro/Src/stm32f7xx_it.c Interrupt handlers
- TIM/TIM_ExtTriggerSynchro/Src/main.c Main program
- TIM/TIM_ExtTriggerSynchro/Src/stm32f7xx_hal_msp.c HAL MSP file
- TIM/TIM_ExtTriggerSynchro/Src/system_stm32f7xx.c STM32F7xx system source file
@par Hardware and Software environment
- This example runs on STM32F767xx/STM32F769xx/STM32F777xx/STM32F779xx devices.
- This example has been tested with STMicroelectronics STM32F769I-EVAL
board and can be easily tailored to any other supported device
and development board.
- STM32F769I-EVAL Set-up
- Connect an external trigger to the TIM1 CH2 PA.09 (pin 43 in CN6 connector).
- Connect the following pins to an oscilloscope to monitor the different waveforms:
- TIM1 CH1 PA.08 (pin 52 in CN6 connector)
- TIM4 CH1 PB.06 pin 18 in CN6 connector
- TIM5 CH1 PA.00 (pin 15 in CN5 connector)
@par How to use it ?
In order to make the program work, you must do the following :
- Open your preferred toolchain
- Rebuild all files and load your image into target memory
- Run the example
*/
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