113 lines
5.4 KiB
Plaintext
113 lines
5.4 KiB
Plaintext
/**
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@page FMC_SDRAM SDRAM memory functionalities example
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@verbatim
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******************************************************************************
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* @file FMC/FMC_SDRAM/readme.txt
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* @author MCD Application Team
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* @brief Description of the FMC_SDRAM example.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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@endverbatim
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@par Example Description
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How to configure the FMC controller to access the SDRAM memory.
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The SDRAM is MT48LC4M32B2B5-6A or IS42S32400F-6BL.
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At the beginning of the main program the HAL_Init() function is called to reset
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all the peripherals, initialize the Flash interface and the systick.
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Then the SystemClock_Config() function is used to configure the system
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clock (SYSCLK) to run at 200 MHz.
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The goal of this example is to explain the different steps to configure the FMC
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and make the SDRAM device ready for access, without using the MSP layer.
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In this example, the SDRAM device is configured and initialized explicitly
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following all initialization sequence steps. After initializing the device, user
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can perform read/write operations on it. A data buffer is written to the SDRAM
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memory, then read back and checked to verify its correctness.
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The user can define the FMC memory bus width by commenting/uncommenting the defines for
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desired configurations in "main.h" :
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FMC_SDRAM_MEM_BUS_WIDTH_8 or FMC_SDRAM_MEM_BUS_WIDTH_16
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The SDRAM memory access are done in 32 bits whatever the configured FMC memory bus width.
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If the data is read correctly from SDRAM, the LED2 is ON, otherwise LED1 blinks :
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- LED1 is Toggled with a period of 200 ms when there is a read or write error.
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- LED1 is Toggled with a period of 1000 ms when there is an error in SDRAM Init process.
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@note - The FMC mode register definition is configured using defines for the external
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memory device mode register, defined in the main header file.
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- The function "BSP_SDRAM_Initialization_Sequence()" is used to program the SDRAM
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device. It is considered as a specific function which depends on the SDRAM device.
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When changing the external device, you may have to apply some changes
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in this function.
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@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
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based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
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a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
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than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
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To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
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@note The application need to ensure that the SysTick time base is always set to 1 millisecond
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to have correct HAL operation.
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@note The STM32F7xx devices can reach a maximum clock frequency of 216MHz but as this example uses SDRAM,
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the system clock is limited to 200MHz. Indeed proper functioning of the SDRAM is only guaranteed
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at a maximum system clock frequency of 200MHz.
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@par Keywords
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Memory, FMC, SDRAM, Read, Write, Initialization, Access
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@Note<74>If the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors,
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<20><><EFBFBD><EFBFBD><EFBFBD>then it is highly recommended to enable the CPU cache and maintain its coherence at application level.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes).
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@Note It is recommended to enable the cache and maintain its coherence, but depending on the use case
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> It is also possible to configure the MPU as "Write through", to guarantee the write access coherence.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Even though the user must manage the cache coherence for read accesses.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4838 <20>Managing memory protection unit (MPU) in STM32 MCUs<55>
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4839 <20>Level 1 cache on STM32F7 Series<65>
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@par Directory contents
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- FMC/FMC_SDRAM/Inc/stm32f7xx_hal_conf.h HAL configuration file
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- FMC/FMC_SDRAM/Inc/main.h Header for main.c module
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- FMC/FMC_SDRAM/Inc/stm32f7xx_it.h Interrupt handlers header file
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- FMC/FMC_SDRAM/Src/main.c Main program
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- FMC/FMC_SDRAM/Src/stm32f7xx_msp.c HAL MSP module
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- FMC/FMC_SDRAM/Src/stm32f7xx_it.c Interrupt handlers
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- FMC/FMC_SDRAM/Src/system_stm32f7xx.c STM32F7xx system source file
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@par Hardware and Software environment
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- This example runs on STM32F779xx/STM32F769xx/STM32F767xx/STM32F777xx devices.
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- This example has been tested with STM32F769I-DISCOVERY board and can be
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easily tailored to any other supported device and development board.
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@par How to use it ?
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In order to make the program work, you must do the following :
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- Open your preferred toolchain
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- Rebuild all files and load your image into target memory
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- Run the example
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*/
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