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/**
@page PWR_EnterStopMode PWR standby example
@verbatim
******************************************************************************
* @file Examples_LL/PWR/PWR_EnterStopMode/readme.txt
* @author MCD Application Team
* @brief Description of the PWR STOP_MAINREGU mode example.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@endverbatim
@par Example Description
How to enter the STOP_MAINREGU mode.
After start-up LED1 is toggling during 5 seconds, then the system automatically
enter in STOP_MAINREGU mode (Final state).
LED1 is used to monitor the system state as follows:
- LED1 toggling : system in RUN mode
- LED1 off : system in STOP_MAINREGU mode
@note To measure the current consumption in STOP_MAINREGU mode, remove JP5 jumper
and connect an ampere meter to JP5 to measure IDD current.
@note This example can not be used in DEBUG mode due to the fact
that the Cortex-M7 core is no longer clocked during low power mode
so debugging features are disabled.
@par Keywords
Power, PWR, stop mode, Interrupt, Low Power
@NoteIf the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors,
then it is highly recommended to enable the CPU cache and maintain its coherence at application level.
The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes).
@Note It is recommended to enable the cache and maintain its coherence, but depending on the use case
It is also possible to configure the MPU as "Write through", to guarantee the write access coherence.
In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable.
Even though the user must manage the cache coherence for read accesses.
Please refer to the AN4838 “Managing memory protection unit (MPU) in STM32 MCUs”
Please refer to the AN4839 “Level 1 cache on STM32F7 Series”
@par Directory contents
- PWR/PWR_EnterStopMode/Inc/stm32f7xx_it.h Interrupt handlers header file
- PWR/PWR_EnterStopMode/Inc/main.h Header for main.c module
- PWR/PWR_EnterStopMode/Inc/stm32_assert.h Template file to include assert_failed function
- PWR/PWR_EnterStopMode/Src/stm32f7xx_it.c Interrupt handlers
- PWR/PWR_EnterStopMode/Src/main.c Main program
- PWR/PWR_EnterStopMode/Src/system_stm32f7xx.c STM32F7xx system source file
@par Hardware and Software environment
- This example runs on STM32F767xx devices.
- This example has been tested with STMicroelectronics NUCLEO-F767ZI
board and can be easily tailored to any other supported device
and development board.
- NUCLEO-F767ZI Set-up
- LED1 connected to PB.0 pin
@par How to use it ?
In order to make the program work, you must do the following :
- Open your preferred toolchain
- Rebuild all files and load your image into target memory
- Run the example
*/
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