/**
@page I2C_OneBoard_AdvCommunication_DMAAndIT I2C (Master DMA Mode)
@verbatim
******************************************************************************
* @file Examples_LL/I2C/I2C_OneBoard_AdvCommunication_DMAAndIT/readme.txt
* @author MCD Application Team
* @brief Description of the I2C_OneBoard_AdvCommunication_DMAAndIT I2C example (Master DMA Mode).
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@endverbatim
@par Example Description
How to exchange data between an I2C master device in DMA mode and an I2C slave
device in interrupt mode. The peripheral is initialized with LL unitary service
functions to optimize for performance and size.
This example guides you through the different configuration steps by mean of LL API
to configure GPIO, DMA and I2C peripherals using only one NUCLEO-F767ZI.
I2C2 Peripheral is configured in Slave mode with EXTI (Clock 400Khz, Own address 7-bit enabled).
I2C1 Peripheral is configured in Master mode with DMA (Clock 400Khz).
GPIO associated to User push-button is linked with EXTI.
LED1 blinks quickly to wait for user-button press.
Example execution:
Press the User push-button to initiate a write request by Master through Handle_I2C_Master_Transmit() or
through Handle_I2C_Master_TransmitReceive() routine depends on Command Code type.
Command code type is decomposed in two categories :
1- Action Command code
a. Type of command which need an action from Slave Device without send any specific answer)
b. I2C sequence is composed like that :
_____________________________________________________________________________________
|_START_|_Slave_Address_|_Wr_|_A_|_Command_Code_BYTE_1_|_A_|_Command_Code_BYTE_2_|_A_|....
________________________________
|_Command_Code_BYTE_M_|_A_|_STOP_|
First of all, through Handle_I2C_Master_Transmit() routine, Master device generate an I2C start condition
with the Slave address and a write bit condition.
When address Slave match code is received on I2C2, an ADDR interrupt occurs.
I2C2 IRQ Handler routine is then checking Address Match Code and direction Write.
This will allow Slave to enter in receiver mode and then acknowledge Master to send the Command code bytes through DMA.
When acknowledge is received on I2C1, DMA transfer the Command code data from flash memory buffer to I2C1 TXDR register.
This will allow Master to transmit a byte to the Slave.
Each time a byte is received on I2C2 (Slave), an RXNE interrupt occurs and byte is stored into an internal buffer
until a STOP condition.
And so each time the Slave acknowledge the byte received,
DMA transfer the next data from flash memory buffer to I2C1 TXDR register until Transfer completed.
Master auto-generate a Stop condition when DMA transfer is achieved.
The STOP condition generate a STOP interrupt and initiate the end of reception on Slave side.
I2C2 IRQ handler and Handle_I2C_Master_Transmit() routine are then clearing the STOP flag in both side.
LED1 is On if data are well sent and the Command Code sent to slave is print in the Terminal I/O.
2- Request Command code :
a. Type of command which need a specific data answer from Slave Device.
b. I2C sequence is composed like that :
_____________________________________________________________________________________
|_START_|_Slave_Address_|_Wr_|_A_|_Command_Code_BYTE_1_|_A_|_Command_Code_BYTE_2_|_A_|....
______________________________________________________________________________
|_Command_Code_BYTE_M_|_A_|_RESTART_|_Slave_Address_|_Rd_|_A_|_Data_BYTE_1_|_A_|...
___________________________________________
|_Data_BYTE_2_|_A_|_Data_BYTE_N_|_NA_|_STOP_|
First of all, through Handle_I2C_Master_TransmitReceive() routine, Master device generate an I2C start condition
with the Slave address and a write bit condition.
When address Slave match code is received on I2C2, an ADDR interrupt occurs.
I2C2 IRQ Handler routine is then checking Address Match Code and direction Write.
This will allow Slave to enter in receiver mode and then acknowledge Master to send the Command code bytes through DMA.
When acknowledge is received on I2C1, DMA transfer the Command code data from flash memory buffer to I2C1 TXDR register.
This will allow Master to transmit a byte to the Slave.
Each time a byte is received on I2C2 (Slave), an RXNE interrupt occurs and byte is stored into an internal buffer
until a RESTART condition.
And so each time the Slave acknowledge the byte received,
DMA transfer the next data from flash memory buffer to I2C1 TXDR register until Transfer completed.
Then Master device generate a RESTART condition with Slave address and a read bit condition.
When address Slave match code is received on I2C2, an ADDR interrupt occurs.
I2C2 IRQ Handler routine is then checking Address Match Code and direction Read.
This will allow Slave to enter in transmitter mode and then send a byte when TXIS interrupt occurs.
When byte is received on I2C1, an RXNE event occurs and DMA transfer data from RXDR register to an internal buffer
until end of transfer.
Master auto-generate a NACK and STOP condition to inform the Slave that the transfer is finished.
The STOP condition generate a STOP interrupt and initiate the end of transmission on Slave side.
I2C2 IRQ handler and Handle_I2C_Master_TransmitReceive() routine are then clearing the STOP flag in both side.
LED1 is On (500 ms) if data are well sent and the Command Code sent to slave is print as follow depending of IDE :
Note that
- When resorting to EWARM IAR IDE:
Command Code is displayed on debugger as follows: View --> Terminal I/O
- When resorting to MDK-ARM KEIL IDE:
Command Code is displayed on debugger as follows: View --> Serial Viewer --> Debug (printf) Viewer
- When resorting to AC6 SW4STM32 IDE:
In Debug configuration window\ Startup, in addition to "monitor reset halt" add the command "monitor arm semihosting enable"
Command Code is displayed on debugger as follows: Window--> Show View--> Console.
After each use cases, the LED1 blinks quickly to wait for a new user-button press to send a new Command code to the Slave device.
In all cases, if an error occurs, LED1 is blinking slowly.
@par Keywords
Connectivity, Communication, I2C, DMA, Interrupt, Master, Slave, Transmission, Reception, Fast mode,
command, acknowledgement
@Note<74>If the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors,
<20><><A0><A0><A0>then it is highly recommended to enable the CPU cache and maintain its coherence at application level.
<0A><><A0><A0><A0><A0>The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes).
@Note It is recommended to enable the cache and maintain its coherence, but depending on the use case
<0A><><A0><A0><A0> It is also possible to configure the MPU as "Write through", to guarantee the write access coherence.
<0A><><A0><A0><A0><A0>In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable.
<0A><><A0><A0><A0><A0>Even though the user must manage the cache coherence for read accesses.
<0A><><A0><A0><A0><A0>Please refer to the AN4838 <20>Managing memory protection unit (MPU) in STM32 MCUs<55>
<0A><><A0><A0><A0><A0>Please refer to the AN4839 <20>Level 1 cache on STM32F7 Series<65>
@par Directory contents
- I2C/I2C_OneBoard_AdvCommunication_DMAAndIT/Inc/stm32f7xx_it.h Interrupt handlers header file
- I2C/I2C_OneBoard_AdvCommunication_DMAAndIT/Inc/main.h Header for main.c module
- I2C/I2C_OneBoard_AdvCommunication_DMAAndIT/Inc/stm32_assert.h Template file to include assert_failed function
- I2C/I2C_OneBoard_AdvCommunication_DMAAndIT/Src/stm32f7xx_it.c Interrupt handlers
- I2C/I2C_OneBoard_AdvCommunication_DMAAndIT/Src/main.c Main program
- I2C/I2C_OneBoard_AdvCommunication_DMAAndIT/Src/system_stm32f7xx.c STM32F7xx system source file
@par Hardware and Software environment
- This example runs on STM32F767xx devices.
- This example has been tested with NUCLEO-F767ZI board and can be
easily tailored to any other supported device and development board.
- NUCLEO-F767ZI Set-up
- Connect GPIOs connected to I2C2 SCL/SDA (PB.10 and PB.11)
to respectively SCL and SDA pins of I2C1 (PB.6 and PB.9).
- I2C2_SCL PB.10 (CN10, pin 32) : connected to I2C1_SCL PB.6 (CN10, pin 13)
- I2C2_SDA PB.11 (CN10, pin 34) : connected to I2C1_SDA PB.9 (CN7, pin 4)
- Launch the program in debug mode to benefit of Terminal I/O information. Press User push-button to initiate a write request by Master
then Slave receive bytes.
@par How to use it ?
In order to make the program work, you must do the following :
- Open your preferred toolchain
- Rebuild all files and load your image into target memory
- Run the example
*/
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