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/**
@page CortexM_MPU Cortex-M7 MPU example
@verbatim
******************************************************************************
* @file CORTEXM/CORTEXM_MPU/readme.txt
* @author MCD Application Team
* @brief Description of the CortexM MPU example.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@endverbatim
@par Example Description
Presentation of the MPU feature. This example configures a memory area as
privileged read-only, and attempts to perform read and write operations in
different modes.
If the access is permitted LED1 is toggling. If the access is not permitted,
a memory management fault is generated and LED2 is ON.
To generate an MPU memory fault exception due to an access right error, uncomment
the following line "PrivilegedReadOnlyArray[0] = 'e';" in the "stm32_mpu.c" file.
@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
@note The application need to ensure that the SysTick time base is always set to 1 millisecond
to have correct HAL operation.
@par Keywords
System, Cortex, Memory regions, Privileged area, permitted access, memory management fault, MPU memory fault
@NoteIf the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors,
then it is highly recommended to enable the CPU cache and maintain its coherence at application level.
The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes).
@Note It is recommended to enable the cache and maintain its coherence, but depending on the use case
It is also possible to configure the MPU as "Write through", to guarantee the write access coherence.
In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable.
Even though the user must manage the cache coherence for read accesses.
Please refer to the AN4838 “Managing memory protection unit (MPU) in STM32 MCUs”
Please refer to the AN4839 “Level 1 cache on STM32F7 Series”
@par Directory contents
- CortexM/MPU/Inc/stm32f7xx_hal_conf.h HAL configuration file
- CortexM/MPU/Inc/stm32f7xx_it.h Interrupt handlers header file
- CortexM/MPU/Inc/main.h Header for main.c module
- CortexM/MPU/Inc/stm32_mpu.h MPU management
- CortexM/MPU/Src/stm32f7xx_it.c Interrupt handlers
- CortexM/MPU/Src/main.c Main program
- CortexM/MPU/Src/system_stm32f7xx.c STM32F7xx system source file
- CortexM/MPU/Src/stm32_mpu.c MPU management
@par Hardware and Software environment
- This example runs on STM32F746ZG devices.
- This example has been tested with NUCLEO-F746ZG Rev.B board and can be
easily tailored to any other supported device and development board.
@par How to use it ?
In order to make the program work, you must do the following :
- Open your preferred toolchain
- Add the required example files
- stm32_mpu.c
- Rebuild all files and load your image into target memory
- Run the example
*/
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