470 lines
30 KiB
ArmAsm
470 lines
30 KiB
ArmAsm
;********************************************************************************
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;* File Name : startup_stm32f746xx.s
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;* Author : MCD Application Team
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;* Description : STM32F746xx devices vector table for MDK-ARM toolchain.
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;* This module performs:
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;* - Set the initial SP
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;* - Set the initial PC == Reset_Handler
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;* - Set the vector table entries with the exceptions ISR address
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;* - Branches to __main in the C library (which eventually
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;* calls main()).
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;* After Reset the CortexM7 processor is in Thread mode,
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;* priority is Privileged, and the Stack is set to Main.
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;* <<< Use Configuration Wizard in Context Menu >>>
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;*******************************************************************************
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;
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;* @attention
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;*
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;* Copyright (c) 2016 STMicroelectronics.
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;* All rights reserved.
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;*
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;* This software is licensed under terms that can be found in the LICENSE file
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;* in the root directory of this software component.
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;* If no LICENSE file comes with this software, it is provided AS-IS.
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;*
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;*******************************************************************************
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; Amount of memory (in bytes) allocated for Stack
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; Tailor this value to your application needs
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; <h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Stack_Size EQU 0x400
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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__initial_sp
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Heap_Size EQU 0x200
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD WWDG_IRQHandler ; Window WatchDog
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DCD PVD_IRQHandler ; PVD through EXTI Line detection
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DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
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DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
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DCD FLASH_IRQHandler ; FLASH
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DCD RCC_IRQHandler ; RCC
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DCD EXTI0_IRQHandler ; EXTI Line0
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DCD EXTI1_IRQHandler ; EXTI Line1
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DCD EXTI2_IRQHandler ; EXTI Line2
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DCD EXTI3_IRQHandler ; EXTI Line3
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DCD EXTI4_IRQHandler ; EXTI Line4
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DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
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DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
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DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
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DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
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DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
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DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
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DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
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DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
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DCD CAN1_TX_IRQHandler ; CAN1 TX
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DCD CAN1_RX0_IRQHandler ; CAN1 RX0
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DCD CAN1_RX1_IRQHandler ; CAN1 RX1
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DCD CAN1_SCE_IRQHandler ; CAN1 SCE
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DCD EXTI9_5_IRQHandler ; External Line[9:5]s
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DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
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DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
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DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
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DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
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DCD TIM2_IRQHandler ; TIM2
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DCD TIM3_IRQHandler ; TIM3
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DCD TIM4_IRQHandler ; TIM4
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DCD I2C1_EV_IRQHandler ; I2C1 Event
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DCD I2C1_ER_IRQHandler ; I2C1 Error
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DCD I2C2_EV_IRQHandler ; I2C2 Event
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DCD I2C2_ER_IRQHandler ; I2C2 Error
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DCD SPI1_IRQHandler ; SPI1
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DCD SPI2_IRQHandler ; SPI2
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DCD USART1_IRQHandler ; USART1
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DCD USART2_IRQHandler ; USART2
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DCD USART3_IRQHandler ; USART3
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DCD EXTI15_10_IRQHandler ; External Line[15:10]s
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DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
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DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
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DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
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DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
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DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
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DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
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DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
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DCD FMC_IRQHandler ; FMC
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DCD SDMMC1_IRQHandler ; SDMMC1
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DCD TIM5_IRQHandler ; TIM5
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DCD SPI3_IRQHandler ; SPI3
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DCD UART4_IRQHandler ; UART4
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DCD UART5_IRQHandler ; UART5
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DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
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DCD TIM7_IRQHandler ; TIM7
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DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
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DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
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DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
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DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
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DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
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DCD ETH_IRQHandler ; Ethernet
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DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
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DCD CAN2_TX_IRQHandler ; CAN2 TX
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DCD CAN2_RX0_IRQHandler ; CAN2 RX0
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DCD CAN2_RX1_IRQHandler ; CAN2 RX1
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DCD CAN2_SCE_IRQHandler ; CAN2 SCE
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DCD OTG_FS_IRQHandler ; USB OTG FS
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DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
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DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
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DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
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DCD USART6_IRQHandler ; USART6
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DCD I2C3_EV_IRQHandler ; I2C3 event
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DCD I2C3_ER_IRQHandler ; I2C3 error
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DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
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DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
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DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
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DCD OTG_HS_IRQHandler ; USB OTG HS
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DCD DCMI_IRQHandler ; DCMI
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DCD 0 ; Reserved
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DCD RNG_IRQHandler ; Rng
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DCD FPU_IRQHandler ; FPU
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DCD UART7_IRQHandler ; UART7
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DCD UART8_IRQHandler ; UART8
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DCD SPI4_IRQHandler ; SPI4
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DCD SPI5_IRQHandler ; SPI5
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DCD SPI6_IRQHandler ; SPI6
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DCD SAI1_IRQHandler ; SAI1
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DCD LTDC_IRQHandler ; LTDC
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DCD LTDC_ER_IRQHandler ; LTDC error
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DCD DMA2D_IRQHandler ; DMA2D
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DCD SAI2_IRQHandler ; SAI2
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DCD QUADSPI_IRQHandler ; QUADSPI
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DCD LPTIM1_IRQHandler ; LPTIM1
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DCD CEC_IRQHandler ; HDMI_CEC
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DCD I2C4_EV_IRQHandler ; I2C4 Event
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DCD I2C4_ER_IRQHandler ; I2C4 Error
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DCD SPDIF_RX_IRQHandler ; SPDIF_RX
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler\
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PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT WWDG_IRQHandler [WEAK]
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EXPORT PVD_IRQHandler [WEAK]
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EXPORT TAMP_STAMP_IRQHandler [WEAK]
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EXPORT RTC_WKUP_IRQHandler [WEAK]
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EXPORT FLASH_IRQHandler [WEAK]
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EXPORT RCC_IRQHandler [WEAK]
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EXPORT EXTI0_IRQHandler [WEAK]
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EXPORT EXTI1_IRQHandler [WEAK]
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EXPORT EXTI2_IRQHandler [WEAK]
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EXPORT EXTI3_IRQHandler [WEAK]
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EXPORT EXTI4_IRQHandler [WEAK]
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EXPORT DMA1_Stream0_IRQHandler [WEAK]
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EXPORT DMA1_Stream1_IRQHandler [WEAK]
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EXPORT DMA1_Stream2_IRQHandler [WEAK]
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EXPORT DMA1_Stream3_IRQHandler [WEAK]
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EXPORT DMA1_Stream4_IRQHandler [WEAK]
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EXPORT DMA1_Stream5_IRQHandler [WEAK]
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EXPORT DMA1_Stream6_IRQHandler [WEAK]
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EXPORT ADC_IRQHandler [WEAK]
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EXPORT CAN1_TX_IRQHandler [WEAK]
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EXPORT CAN1_RX0_IRQHandler [WEAK]
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EXPORT CAN1_RX1_IRQHandler [WEAK]
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EXPORT CAN1_SCE_IRQHandler [WEAK]
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EXPORT EXTI9_5_IRQHandler [WEAK]
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EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
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EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
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EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
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EXPORT TIM1_CC_IRQHandler [WEAK]
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EXPORT TIM2_IRQHandler [WEAK]
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EXPORT TIM3_IRQHandler [WEAK]
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EXPORT TIM4_IRQHandler [WEAK]
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EXPORT I2C1_EV_IRQHandler [WEAK]
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EXPORT I2C1_ER_IRQHandler [WEAK]
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EXPORT I2C2_EV_IRQHandler [WEAK]
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EXPORT I2C2_ER_IRQHandler [WEAK]
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EXPORT SPI1_IRQHandler [WEAK]
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EXPORT SPI2_IRQHandler [WEAK]
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EXPORT USART1_IRQHandler [WEAK]
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EXPORT USART2_IRQHandler [WEAK]
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EXPORT USART3_IRQHandler [WEAK]
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EXPORT EXTI15_10_IRQHandler [WEAK]
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EXPORT RTC_Alarm_IRQHandler [WEAK]
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EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
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EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
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EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
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EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
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EXPORT TIM8_CC_IRQHandler [WEAK]
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EXPORT DMA1_Stream7_IRQHandler [WEAK]
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EXPORT FMC_IRQHandler [WEAK]
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EXPORT SDMMC1_IRQHandler [WEAK]
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EXPORT TIM5_IRQHandler [WEAK]
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EXPORT SPI3_IRQHandler [WEAK]
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EXPORT UART4_IRQHandler [WEAK]
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EXPORT UART5_IRQHandler [WEAK]
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EXPORT TIM6_DAC_IRQHandler [WEAK]
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EXPORT TIM7_IRQHandler [WEAK]
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EXPORT DMA2_Stream0_IRQHandler [WEAK]
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EXPORT DMA2_Stream1_IRQHandler [WEAK]
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EXPORT DMA2_Stream2_IRQHandler [WEAK]
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EXPORT DMA2_Stream3_IRQHandler [WEAK]
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EXPORT DMA2_Stream4_IRQHandler [WEAK]
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EXPORT ETH_IRQHandler [WEAK]
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EXPORT ETH_WKUP_IRQHandler [WEAK]
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EXPORT CAN2_TX_IRQHandler [WEAK]
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EXPORT CAN2_RX0_IRQHandler [WEAK]
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EXPORT CAN2_RX1_IRQHandler [WEAK]
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EXPORT CAN2_SCE_IRQHandler [WEAK]
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EXPORT OTG_FS_IRQHandler [WEAK]
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EXPORT DMA2_Stream5_IRQHandler [WEAK]
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EXPORT DMA2_Stream6_IRQHandler [WEAK]
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EXPORT DMA2_Stream7_IRQHandler [WEAK]
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EXPORT USART6_IRQHandler [WEAK]
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EXPORT I2C3_EV_IRQHandler [WEAK]
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EXPORT I2C3_ER_IRQHandler [WEAK]
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EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
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EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
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EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
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EXPORT OTG_HS_IRQHandler [WEAK]
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EXPORT DCMI_IRQHandler [WEAK]
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EXPORT RNG_IRQHandler [WEAK]
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EXPORT FPU_IRQHandler [WEAK]
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EXPORT UART7_IRQHandler [WEAK]
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EXPORT UART8_IRQHandler [WEAK]
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EXPORT SPI4_IRQHandler [WEAK]
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EXPORT SPI5_IRQHandler [WEAK]
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EXPORT SPI6_IRQHandler [WEAK]
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EXPORT SAI1_IRQHandler [WEAK]
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EXPORT LTDC_IRQHandler [WEAK]
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EXPORT LTDC_ER_IRQHandler [WEAK]
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EXPORT DMA2D_IRQHandler [WEAK]
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EXPORT SAI2_IRQHandler [WEAK]
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EXPORT QUADSPI_IRQHandler [WEAK]
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EXPORT LPTIM1_IRQHandler [WEAK]
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EXPORT CEC_IRQHandler [WEAK]
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EXPORT I2C4_EV_IRQHandler [WEAK]
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EXPORT I2C4_ER_IRQHandler [WEAK]
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EXPORT SPDIF_RX_IRQHandler [WEAK]
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WWDG_IRQHandler
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PVD_IRQHandler
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TAMP_STAMP_IRQHandler
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RTC_WKUP_IRQHandler
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FLASH_IRQHandler
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RCC_IRQHandler
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EXTI0_IRQHandler
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EXTI1_IRQHandler
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EXTI2_IRQHandler
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EXTI3_IRQHandler
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EXTI4_IRQHandler
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DMA1_Stream0_IRQHandler
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DMA1_Stream1_IRQHandler
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DMA1_Stream2_IRQHandler
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DMA1_Stream3_IRQHandler
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DMA1_Stream4_IRQHandler
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DMA1_Stream5_IRQHandler
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DMA1_Stream6_IRQHandler
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ADC_IRQHandler
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CAN1_TX_IRQHandler
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CAN1_RX0_IRQHandler
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CAN1_RX1_IRQHandler
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CAN1_SCE_IRQHandler
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EXTI9_5_IRQHandler
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TIM1_BRK_TIM9_IRQHandler
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TIM1_UP_TIM10_IRQHandler
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TIM1_TRG_COM_TIM11_IRQHandler
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TIM1_CC_IRQHandler
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TIM2_IRQHandler
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TIM3_IRQHandler
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TIM4_IRQHandler
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I2C1_EV_IRQHandler
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I2C1_ER_IRQHandler
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I2C2_EV_IRQHandler
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I2C2_ER_IRQHandler
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SPI1_IRQHandler
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SPI2_IRQHandler
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USART1_IRQHandler
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USART2_IRQHandler
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USART3_IRQHandler
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EXTI15_10_IRQHandler
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RTC_Alarm_IRQHandler
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OTG_FS_WKUP_IRQHandler
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TIM8_BRK_TIM12_IRQHandler
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TIM8_UP_TIM13_IRQHandler
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TIM8_TRG_COM_TIM14_IRQHandler
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TIM8_CC_IRQHandler
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DMA1_Stream7_IRQHandler
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FMC_IRQHandler
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SDMMC1_IRQHandler
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TIM5_IRQHandler
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SPI3_IRQHandler
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UART4_IRQHandler
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UART5_IRQHandler
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TIM6_DAC_IRQHandler
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TIM7_IRQHandler
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DMA2_Stream0_IRQHandler
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DMA2_Stream1_IRQHandler
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DMA2_Stream2_IRQHandler
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DMA2_Stream3_IRQHandler
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DMA2_Stream4_IRQHandler
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ETH_IRQHandler
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ETH_WKUP_IRQHandler
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CAN2_TX_IRQHandler
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CAN2_RX0_IRQHandler
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CAN2_RX1_IRQHandler
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CAN2_SCE_IRQHandler
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OTG_FS_IRQHandler
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DMA2_Stream5_IRQHandler
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DMA2_Stream6_IRQHandler
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DMA2_Stream7_IRQHandler
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USART6_IRQHandler
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I2C3_EV_IRQHandler
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I2C3_ER_IRQHandler
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OTG_HS_EP1_OUT_IRQHandler
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OTG_HS_EP1_IN_IRQHandler
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OTG_HS_WKUP_IRQHandler
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OTG_HS_IRQHandler
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DCMI_IRQHandler
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RNG_IRQHandler
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FPU_IRQHandler
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UART7_IRQHandler
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UART8_IRQHandler
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SPI4_IRQHandler
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SPI5_IRQHandler
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SPI6_IRQHandler
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SAI1_IRQHandler
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LTDC_IRQHandler
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LTDC_ER_IRQHandler
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DMA2D_IRQHandler
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SAI2_IRQHandler
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QUADSPI_IRQHandler
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LPTIM1_IRQHandler
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CEC_IRQHandler
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I2C4_EV_IRQHandler
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I2C4_ER_IRQHandler
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SPDIF_RX_IRQHandler
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B .
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ENDP
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ALIGN
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;*******************************************************************************
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; User Stack and Heap initialization
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;*******************************************************************************
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IF :DEF:__MICROLIB
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EXPORT __initial_sp
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EXPORT __heap_base
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EXPORT __heap_limit
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ELSE
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IMPORT __use_two_region_memory
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EXPORT __user_initial_stackheap
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__user_initial_stackheap
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LDR R0, = Heap_Mem
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LDR R1, =(Stack_Mem + Stack_Size)
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LDR R2, = (Heap_Mem + Heap_Size)
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LDR R3, = Stack_Mem
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BX LR
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ALIGN
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ENDIF
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END
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