132 lines
5.6 KiB
Plaintext
132 lines
5.6 KiB
Plaintext
/**
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@page TIM_TimeBase Time Base example
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@verbatim
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******************************************************************************
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* @file TIM/TIM_TimeBase/readme.txt
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* @author MCD Application Team
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* @brief Description of the TIM Time Base example
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2018 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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@endverbatim
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@par Example Description
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Configuration of the TIM peripheral to generate a timebase of
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one second with the corresponding interrupt request.
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In this example, the code is executed from QSPI external memory while data are in internal
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SRAM memory.
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In this example TIM3 input clock (TIM3CLK) is set to APB1 clock (PCLK1) x2,
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since APB1 prescaler is equal to 4.
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TIM3CLK = PCLK1*2
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PCLK1 = HCLK/4
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=> TIM3CLK = HCLK/2 = SystemCoreClock/2
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To get TIM3 counter clock at 10 KHz, the Prescaler is computed as follows:
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Prescaler = (TIM3CLK / TIM3 counter clock) - 1
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Prescaler = ((SystemCoreClock/2) /10 KHz) - 1
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SystemCoreClock is set to 216 MHz for STM32F7xx Devices.
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The TIM3 ARR register value is equal to 10000 - 1,
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Update rate = TIM3 counter clock / (Period + 1) = 1 Hz,
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So the TIM3 generates an interrupt each 1 s
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When the counter value reaches the auto-reload register value, the TIM update
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interrupt is generated and, in the handler routine, pin PB1 (connected to LED6 on board STM32F7308-DISCO)
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is toggled at the following frequency: 0.5Hz.
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In case of error, LED5 is turned ON.
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@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
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based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
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a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
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than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
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To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
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@note The application need to ensure that the SysTick time base is always set to 1 millisecond
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to have correct HAL operation.
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@par Keywords
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Timer, TIM, Time Base, Interrupt, Clock source
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@Note<74>If the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors,
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<20><><EFBFBD><EFBFBD><EFBFBD>then it is highly recommended to enable the CPU cache and maintain its coherence at application level.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes).
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@Note It is recommended to enable the cache and maintain its coherence, but depending on the use case
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> It is also possible to configure the MPU as "Write through", to guarantee the write access coherence.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Even though the user must manage the cache coherence for read accesses.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4838 <20>Managing memory protection unit (MPU) in STM32 MCUs<55>
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4839 <20>Level 1 cache on STM32F7 Series<65>
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@par Directory contents
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- TIM/TIM_TimeBase/Inc/stm32f7xx_hal_conf.h HAL configuration file
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- TIM/TIM_TimeBase/Inc/stm32f7xx_it.h Interrupt handlers header file
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- TIM/TIM_TimeBase/Inc/main.h Header for main.c module
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- TIM/TIM_TimeBase/Src/stm32f7xx_it.c Interrupt handlers
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- TIM/TIM_TimeBase/Src/main.c Main program
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- TIM/TIM_TimeBase/Src/stm32f7xx_hal_msp.c HAL MSP file
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- TIM/TIM_TimeBase/Src/system_stm32f7xx.c STM32F7xx system source file
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@par Hardware and Software environment
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- This example runs on STM32F730xx devices.
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- In this example, the clock is set to 216 MHz.
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- This example has been tested with STMicroelectronics STM32F7308-DISCO
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board and can be easily tailored to any other supported device
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and development board.
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- STM32F7308-DISCO Set-up
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- Use LED6 connected to PB1 pin (LED6) and connect it on an oscilloscope
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to show the Time Base signal.
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@par How to use it ?
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In order to make the program work, you must do the following:
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1. Select required configuration in memory.h in Templates\ExtMem_Boot\Inc.
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The default configuration is the right one:
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- DATA_AREA set to USE_INTERNAL_SRAM
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- CODE_AREA set to USE_QSPI
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2. Program the internal Flash with the ExtMem_Boot (see below).
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3. Program the external memory with this example (see below).
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4. Start debugging user example or reset for free running.
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In order to load the ExtMem_Boot code :
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- Open your preferred toolchain :
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- Open the Project
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- Rebuild all files
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- Load project image
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In order to load this example to the external memory :
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- Open your preferred toolchain
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- Rebuild all files.
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- Run & debug the program:
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- Using EWARM or MDK-ARM : Load project image from the IDE: Project->Debug
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- Using SW4STM32 :
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- Open the STM32CubeProgrammer tool
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- Select the QSPI external flash loader "MX25L512G_STM32F7308-DISCO"
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- From Erasing & Programming menu, browse and open the output binary file relative to this example
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- Load the file into the external QSPI flash using "Start Programming" at the address APPLICATION_ADDRESS (0x90000000)
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- Run & debug the program:
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*/
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