113 lines
5.5 KiB
Plaintext
113 lines
5.5 KiB
Plaintext
/**
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@page RCC_ClockConfig RCC Clock Config example
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@verbatim
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******************************************************************************
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* @file RCC/RCC_ClockConfig/readme.txt
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* @author MCD Application Team
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* @brief Description of the RCC Clock Config example.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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@endverbatim
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@par Example Description
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Configuration of the system clock (SYSCLK) and modification of the clock settings in Run mode, using the RCC HAL API.
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In this example, after startup SYSCLK is configured to the max frequency using the PLL with
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HSE as clock source, the User push-button (connected to EXTI_Line15_10) will be
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used to change the PLL source:
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- from HSI to HSE bypass
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- from HSE bypass to HSI
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@note In HSE bypass mode, input clock will come from the MCO from
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ST_LINK MCU. This frequency cannot be changed, and it is fixed
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at 8 MHz. To use MCO from ST_LINK you need to check the Board
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User Manual to know how to connect the MCO pin to the STM32 device.
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Each time the User push-button is pressed; EXTI_Line15_10 interrupt is generated and in the ISR
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the PLL oscillator source is checked using __HAL_RCC_GET_PLL_OSCSOURCE() macro:
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- If the HSE bypass oscillator is selected as PLL source, the following steps will be followed to switch
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the PLL source to HSI oscillator:
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a- Switch the system clock source to HSE bypass to allow modification of the PLL configuration
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b- Enable HSI Oscillator, select it as PLL source and finally activate the PLL
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c- Select the PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
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d- Disable the HSE bypass oscillator (optional, if the HSE bypass is no more needed by the application)
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- If the HSI oscillator is selected as PLL source, the following steps will be followed to switch
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the PLL source to HSE bypass oscillator:
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a- Switch the system clock source to HSI to allow modification of the PLL configuration
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b- Enable HSE bypass Oscillator, select it as PLL source and finally activate the PLL
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c- Select the PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
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d- Disable the HSI oscillator (optional, if the HSI is no more needed by the application)
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In this example the SYSCLK / 1 is outputted on the MCO1 pin(PA.08).
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=> PA.08 connected to pin 23 on CN12 connector
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LED1 is toggled with a timing defined by the HAL_Delay() API.
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LED3 toggles in case of error handler.
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@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
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based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
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a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
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than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
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To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
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@note The application need to ensure that the SysTick time base is always set to 1 millisecond
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to have correct HAL operation.
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@par Keywords
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RCC, System, Clock Configuration, HSE bypass mode, HSI, System clock, Oscillator, PLL
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@Note<74>If the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors,
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<20><><EFBFBD><EFBFBD><EFBFBD>then it is highly recommended to enable the CPU cache and maintain its coherence at application level.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes).
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@Note It is recommended to enable the cache and maintain its coherence, but depending on the use case
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> It is also possible to configure the MPU as "Write through", to guarantee the write access coherence.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Even though the user must manage the cache coherence for read accesses.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4838 <20>Managing memory protection unit (MPU) in STM32 MCUs<55>
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4839 <20>Level 1 cache on STM32F7 Series<65>
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@par Directory contents
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- RCC/RCC_ClockConfig/Inc/stm32f7xx_hal_conf.h HAL configuration file
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- RCC/RCC_ClockConfig/Inc/stm32f7xx_it.h Interrupt handlers header file
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- RCC/RCC_ClockConfig/Inc/main.h Header for main.c module
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- RCC/RCC_ClockConfig/Src/stm32f7xx_it.c Interrupt handlers
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- RCC/RCC_ClockConfig/Src/main.c Main program
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- RCC/RCC_ClockConfig/Src/system_stm32f7xx.c STM32F7xx system source file
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@par Hardware and Software environment
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- This example runs on STM32F722xx/STM32F723xx/STM32F732xx/STM32F733xx devices.
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- This example has been tested with STM32F722ZE-Nucleo
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board and can be easily tailored to any other supported device
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and development board.
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@par How to use it ?
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In order to make the program work, you must do the following :
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- Open your preferred toolchain
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- Rebuild all files and load your image into target memory
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- Run the example
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*/
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