/**
@page FreeRTOS_Timers FreeRTOS Timers application
@verbatim
******************** (C) COPYRIGHT 2016 STMicroelectronics *******************
* @file FreeRTOS/FreeRTOS_Timers/readme.txt
* @author MCD Application Team
* @brief Description of the FreeRTOS Timers application.
******************************************************************************
*
* @attention
*
* Copyright (c) 2017 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@endverbatim
@par Description
How to use timers of CMSIS RTOS API.
This application creates a thread that toggles LED2 every 400 ms, and a periodic
timer that calls a callback function every 200 ms to toggle the LED1.
@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
based on variable incremented in HAL time base ISR. This implies that if HAL_Delay() is called from
a peripheral ISR process, then the HAL time base interrupt must have higher priority (numerically lower)
than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
To change the HAL time base interrupt priority you have to use HAL_NVIC_SetPriority() function.
@note The application needs to ensure that the HAL time base is always set to 1 millisecond
to have correct HAL operation.
@note The FreeRTOS heap size configTOTAL_HEAP_SIZE defined in FreeRTOSConfig.h is set according to
the OS resources memory requirements of the application with +10% margin and rounded to the
upper Kbyte boundary.
For more details about FreeRTOS implementation on STM32Cube, please refer to UM1722 "Developing Applications
on STM32Cube with RTOS".
@par Keywords
RTOS, FreeRTOS, Threading, Timer
@Note<74>If the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors,
<20><><A0><A0><A0>then it is highly recommended to enable the CPU cache and maintain its coherence at application level.
<0A><><A0><A0><A0><A0>The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes).
@Note It is recommended to enable the cache and maintain its coherence, but depending on the use case
<0A><><A0><A0><A0> It is also possible to configure the MPU as "Write through", to guarantee the write access coherence.
<0A><><A0><A0><A0><A0>In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable.
<0A><><A0><A0><A0><A0>Even though the user must manage the cache coherence for read accesses.
<0A><><A0><A0><A0><A0>Please refer to the AN4838 <20>Managing memory protection unit (MPU) in STM32 MCUs<55>
<0A><><A0><A0><A0><A0>Please refer to the AN4839 <20>Level 1 cache on STM32F7 Series<65>
@par Directory contents
- FreeRTOS/FreeRTOS_Timers/Inc/main.h Main program header file
- FreeRTOS/FreeRTOS_Timers/Inc/stm32f7xx_hal_conf.h HAL Library Configuration file
- FreeRTOS/FreeRTOS_Timers/Inc/stm32f7xx_it.h Interrupt handlers header file
- FreeRTOS/FreeRTOS_Timers/Inc/FreeRTOSConfig.h FreeRTOS Configuration file
- FreeRTOS/FreeRTOS_Timers/Src/main.c Main program
- FreeRTOS/FreeRTOS_Timers/Src/stm32f7xx_it.c Interrupt handlers
@par Hardware and Software environment
- This application runs on STM32F756xx/STM32F746xx devices.
- This example has been tested with STM327x6G_EVAL evaluation board and can be
easily tailored to any other supported device and development board.
- STM327x6G_EVAL Set-up
- Ensure that JP24 is in position 2-3 to use LED1.
@par How to use it ?
In order to make the program work, you must do the following :
- Open your preferred toolchain
- Rebuild all files and load your image into target memory
- Run the example
*/
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