94 lines
4.3 KiB
Plaintext
94 lines
4.3 KiB
Plaintext
/**
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@page QSPI_ExecuteInPlace QSPI execute in place example
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@verbatim
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******************************************************************************
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* @file QSPI/QSPI_ExecuteInPlace/readme.txt
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* @author MCD Application Team
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* @brief Description of the code execution from QSPI memory example.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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@endverbatim
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@par Example Description
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How to execute code from QSPI memory after code loading.
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This example describes how to execute a part of the code from a QSPI memory. To do this,
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a section is created where the function is stored.
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During startup, the QSPI memory is erased. Data are then copied from the initialization
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section of the flash to the QSPI memory. Finally, the QSPI is configured in memory-mapped
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mode and the code is executed in a forever loop.
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LED1 is toggled in a forever loop.
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As soon as an error is returned by HAL API, LED1 is turned on.
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In this example, HCLK is configured at 216 MHz.
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@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
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based on a variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
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a peripheral ISR process, the SysTick interrupt must have higher priority (numerically lower)
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than the peripheral interrupt. Otherwise, the caller ISR process will be blocked.
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To change the SysTick interrupt priority, you have to use the HAL_NVIC_SetPriority() function.
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@note The application needs to ensure that the SysTick time base is always set to 1 millisecond,
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to have correct HAL operation.
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@par Keywords
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Memory, QUADSPI, Execute in place, Erase, section, sector, memory-mapped mode
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@Note<74>If the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors,
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<20><><EFBFBD><EFBFBD><EFBFBD>then it is highly recommended to enable the CPU cache and maintain its coherence at application level.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes).
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@Note It is recommended to enable the cache and maintain its coherence, but depending on the use case
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> It is also possible to configure the MPU as "Write through", to guarantee the write access coherence.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Even though the user must manage the cache coherence for read accesses.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4838 <20>Managing memory protection unit (MPU) in STM32 MCUs<55>
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4839 <20>Level 1 cache on STM32F7 Series<65>
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@par Directory contents
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- QSPI/QSPI_ExecuteInPlace/Inc/stm32f7xx_hal_conf.h HAL configuration file
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- QSPI/QSPI_ExecuteInPlace/Inc/stm32f7xx_it.h Interrupt handlers header file
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- QSPI/QSPI_ExecuteInPlace/Inc/main.h Header for main.c module
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- QSPI/QSPI_ExecuteInPlace/Src/stm32f7xx_it.c Interrupt handlers
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- QSPI/QSPI_ExecuteInPlace/Src/main.c Main program
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- QSPI/QSPI_ExecuteInPlace/Src/system_stm32f7xx.c STM32F7xx system source file
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- QSPI/QSPI_ExecuteInPlace/Src/stm32f7xx_hal_msp.c HAL MSP file
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@par Hardware and Software environment
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- This example runs on STM32F7xx devices.
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- This example has been tested on STM32746G-DISCOVERY rev B board containing the N25Q128A QSPI memory
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and can be easily tailored to any other supported device and/or development board .
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However, it does not work on the STM32746G-DISCOVERY Rev C03 board, as it contains the W25Q128J QSPI memory.
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- STM32746G-DISCOVERY Set-up :
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- Board is configured by default to access N25Q128A QSPI memory
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@par How to use it ?
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In order to make the program work, you must do the following :
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- Open your preferred toolchain
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- Rebuild all files and load your image into target memory
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- Run the example
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*/
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