112 lines
5.3 KiB
Plaintext
112 lines
5.3 KiB
Plaintext
/**
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@page FMC_SDRAM_LowPower SDRAM memory functionalities example
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@verbatim
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******************************************************************************
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* @file FMC/FMC_SDRAM_LowPower/readme.txt
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* @author MCD Application Team
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* @brief Description of the FMC_SDRAM_LowPower example.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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@endverbatim
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@par Example Description
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How to configure the FMC controller to access the SDRAM memory in low power
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mode (SDRAM Self Refresh mode).
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The SDRAM is MT48LC4M32B2B5-6A.
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It gives a simple application of the FMC SDRAM low power mode use (self refresh mode)
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while the MCU is in a low power mode (STOP mode).
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At the beginning of the main program the HAL_Init() function is called to reset
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all the peripherals, initialize the Flash interface and the systick.
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Then the SystemClock_Config() function is used to configure the system
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clock (SYSCLK) to run at 200 MHz.
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The purpose is to show how the SDRAM can retain data written after entering STOP mode.
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STOP mode is a CPU low power mode which stops all peripherals clocks in the 1.2V
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domain. Only internal SRAM and registers content are preserved in this mode.
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After SDRAM initialization, the data is written to the memory and a "self refresh"
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command is sent to the SDRAM. The program waits for User push-button to be pushed
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to enter the CPU in STOP mode, the LED1 is then turned ON.
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The wakeup from STOP mode is done when pushing User push-button and the CPU returns
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to RUN mode. At this time, the system clock is reconfigured using the function
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SystemClock_Config(). The LED1 is then turned OFF.
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Finally, a "normal mode" command is send to SDRAM memory to exit self refresh mode.
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The data written to SDRAM is read back and checked.
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LED1 is used to indicate the system state as following:
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- LED1 ON: CPU enters STOP mode.
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- LED1 OFF: the CPU is in RUN mode.
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- LED1 blinks with a 1s period : correct data transfer (PASS).
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- LED1 blinks with a 200ms period : incorrect data transfer (FAIL).
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@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
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based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from
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a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower)
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than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
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To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function.
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@note The application need to ensure that the SysTick time base is always set to 1 millisecond
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to have correct HAL operation.
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@note The STM32F7xx devices can reach a maximum clock frequency of 216MHz but as this example uses SDRAM,
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the system clock is limited to 200MHz. Indeed proper functioning of the SDRAM is only guaranteed
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at a maximum system clock frequency of 200MHz.
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@par Keywords
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Memory, FMC, SDRAM, Read, Write, Initialization, Access, Low power, Self Refresh, Stop mode,
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@Note<74>If the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors,
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<20><><EFBFBD><EFBFBD><EFBFBD>then it is highly recommended to enable the CPU cache and maintain its coherence at application level.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes).
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@Note It is recommended to enable the cache and maintain its coherence, but depending on the use case
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> It is also possible to configure the MPU as "Write through", to guarantee the write access coherence.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Even though the user must manage the cache coherence for read accesses.
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4838 <20>Managing memory protection unit (MPU) in STM32 MCUs<55>
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4839 <20>Level 1 cache on STM32F7 Series<65>
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@par Directory contents
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- FMC/FMC_SDRAM_LowPower/Inc/stm32f7xx_hal_conf.h HAL configuration file
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- FMC/FMC_SDRAM_LowPower/Inc/main.h Header for main.c module
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- FMC/FMC_SDRAM_LowPower/Inc/stm32f7xx_it.h Interrupt handlers header file
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- FMC/FMC_SDRAM_LowPower/Src/main.c Main program
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- FMC/FMC_SDRAM_LowPower/Src/stm32f7xx_it.c Interrupt handlers
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- FMC/FMC_SDRAM_LowPower/Src/system_stm32f7xx.c STM32F7xx system source file
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@par Hardware and Software environment
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- This example runs on STM32F756xx/STM32F746xx devices.
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- This example has been tested with STM32746G-DISCOVERY board and can be
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easily tailored to any other supported device and development board.
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@par How to use it ?
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In order to make the program work, you must do the following :
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- Open your preferred toolchain
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- Rebuild all files and load your image into target memory
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- Run the example
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*/
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