This example describes how to customize the HAL time base using RTC alarm instead
of Systick as main source of time base. The User push-button (connected to EXTI Line[15:10])
will be used to Suspend or Resume tick increment.
Each time, the User push-button is pressed; EXTI15_10 interrupt is generated and in the ISR
the uwIncrementState is checked:
1- If the uwIncrementState = 0: the tick increment is suspended by calling
HAL_SuspendTick() API (RTC alarm interrupt is disabled).
2- If the uwIncrementState = 1: the tick increment is Resumed by calling
HAL_ResumeTick() API(RTC alarm interrupt is enabled).
The alarm is configured to assert an interrupt when the RTC reaches 1 ms
The example brings, in user file, a new implementation of the following HAL weak functions:
HAL_InitTick()
HAL_SuspendTick()
HAL_ResumeTick()
This implementation will overwrite native implementation in stm32f7xx_hal.c
and so user functions will be invoked instead when called.
The following time base functions are kept as implemented natively:
HAL_IncTick()
HAL_Delay()
When user pushes the User push-button, the Tick increment is suspended if it is already
enabled, else it will be resumed.
In an infinite loop, LED1 toggles spaced out over 1s delay.
@note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds)
based on variable incremented in HAL time base ISR. This implies that if HAL_Delay() is called from
a peripheral ISR process, then the HAL time base interrupt must have higher priority (numerically lower)
than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
To change the HAL time base interrupt priority you have to use HAL_NVIC_SetPriority() function.
@note The application needs to ensure that the HAL time base is always set to 1 millisecond
to have correct HAL operation.
@par Keywords
System, RTC Alarm, Time base, HAL
@Note<74>If the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors,
<20><><EFBFBD><EFBFBD><EFBFBD>then it is highly recommended to enable the CPU cache and maintain its coherence at application level.
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes).
@Note It is recommended to enable the cache and maintain its coherence, but depending on the use case
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> It is also possible to configure the MPU as "Write through", to guarantee the write access coherence.
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable.
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Even though the user must manage the cache coherence for read accesses.
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4838 <20>Managing memory protection unit (MPU) in STM32 MCUs<55>
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Please refer to the AN4839 <20>Level 1 cache on STM32F7 Series<65>
@par Directory contents
- HAL/HAL_TimeBase_RTC_ALARM/Inc/stm32f7xx_hal_conf.h HAL configuration file
