107 lines
3.8 KiB
Plaintext
107 lines
3.8 KiB
Plaintext
/**
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@page TIM_CascadeSynchro Timers Synchronization example
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@verbatim
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******************** (C) COPYRIGHT 2017 STMicroelectronics *******************
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* @file TIM/TIM_CascadeSynchro/readme.txt
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* @author MCD Application Team
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* @brief How to command 2 Timers as slaves (TIM3 & TIM4) using a Timer
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* as master (TIM2)
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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@endverbatim
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@par Example Description
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This example shows how to synchronize TIM2 and Timers (TIM3 and TIM4) in cascade mode.
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Timers synchronisation in cascade mode :
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___________ ___________ ___________
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| MASTER |TRGO_Update ITR1 | SLAVE 1 | ITR2 | SLAVE 2 |
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| TIM2 |-------------------| TIM3 |------------| TIM4 |
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|___________| |___________| |___________|
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1/ TIM2 is configured as Master Timer:
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- PWM Mode is used
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- The TIM2 Update event is used as Trigger Output
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2)TIM3 is slave for TIM2 and Master for TIM4,
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- PWM Mode is used
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- The ITR1(TIM2) is used as input trigger
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- Gated mode is used, so start and stop of slave counter
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are controlled by the Master trigger output signal(TIM2 update event).
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- The TIM3 Update event is used as Trigger Output.
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3)TIM4 is slave for TIM3,
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- PWM Mode is used
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- The ITR2(TIM3) is used as input trigger
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- Gated mode is used, so start and stop of slave counter are controlled by the
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Master trigger output signal(TIM3 update event).
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The TIM2 counter clock is 180 MHz.
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The Master Timer TIM2 is running at:
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TIM2 frequency = TIM2 counter clock / (TIM2_Period + 1) = 351.562 KHz and
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a the duty cycle equal to: TIM2_CCR1/(TIM2_ARR + 1) = 25%
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The TIM3 is running at:
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(TIM2 frequency)/ (TIM3 period +1) = 87.891 KHz and
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a duty cycle equal to TIM3_CCR1/(TIM3_ARR + 1) = 25%
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The TIM4 is running at:
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(TIM3 frequency)/ (TIM4 period +1) = 21.973 KHz and
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a duty cycle equal to TIM4_CCR1/(TIM4_ARR + 1) = 25%
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The PWM waveform can be displayed using an oscilloscope.
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@par Keywords
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Timers, PWM, Cascade Synchronization, Master, Slave, Duty Cycle, Waveform, Oscilloscope, Output, Signal
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@par Directory contents
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- TIM/TIM_CascadeSynchro/Inc/stm32f4xx_hal_conf.h HAL configuration file
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- TIM/TIM_CascadeSynchro/Inc/stm32f4xx_it.h Interrupt handlers header file
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- TIM/TIM_CascadeSynchro/Inc/main.h Header for main.c module
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- TIM/TIM_CascadeSynchro/Src/stm32f4xx_it.c Interrupt handlers
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- TIM/TIM_CascadeSynchro/Src/main.c Main program
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- TIM/TIM_CascadeSynchro/Src/stm32f4xx_hal_msp.c HAL MSP file
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- TIM/TIM_CascadeSynchro/Src/system_stm32f4xx.c STM32F4xx system source file
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@par Hardware and Software environment
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- This example runs on STM32F446xx devices.
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- This example has been tested with STM32446E-EVAL board and can be
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easily tailored to any other supported device and development board.
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- STM32446E-EVAL Set-up
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Connect the following pins to an oscilloscope to monitor the different waveforms:
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- TIM2 CH1 (PA.00)
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- TIM3 CH1 (PC.06)
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- TIM4 CH3 (PB.08)
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@par How to use it ?
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In order to make the program work, you must do the following :
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- Open your preferred toolchain
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- Rebuild all files: Project->Rebuild all
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- Load project image: Project->Download and Debug
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- Run program: Debug->Go(F5)
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*/
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