Commit Graph

25 Commits

Author SHA1 Message Date
Rania JMAI 590ddf74a7 [HAL] Upload new fixes 2024-10-07 10:51:18 +01:00
karim ac682c6bc3 [HAL] Upload new fixes 2024-09-04 16:42:18 +01:00
Tasnim 42472d601c Release v1.8.6 2024-08-02 11:53:51 +01:00
Tasnim 3d53398c29 [HAL] Upload new fixes 2024-07-01 14:13:52 +01:00
karim e520340527 [HAL] Upload new fixes 2024-06-20 14:15:21 +01:00
karim 7b479bfd21 [HAL] Upload new fixes 2024-05-22 16:50:01 +01:00
Rania JMAI 67f128d83b [BSP] Replace 'BSP/Components/<component>' folders by submodules 2024-04-29 15:06:41 +01:00
Tasnim bf08129dc1 [HAL][LL] Upload new fixes 2024-04-26 12:52:40 +01:00
Rania JMAI 7dadc1a490 [HAL] Upload new fixes 2024-04-01 13:47:35 +01:00
Tasnim 726163ed2a [CMSIS] Upload new fixes 2024-02-27 09:06:36 +01:00
Tasnim 1ef7b664c5 [HAL] Upload new fixes 2024-01-25 16:27:38 +01:00
Ali Labbene 1386f613e0 [BSP] Replace 'BSP/<board>' folders by submodules 2024-01-15 15:37:15 +01:00
Ali Labbene 7de79e327d [HAL] Upload new fixes 2023-12-18 12:48:49 +01:00
Rania JMAI e226c47ca6 [HAL] Upload new fixes 2023-11-20 10:14:04 +01:00
Ali Labbene 61998a7993 [CMSIS][HAL] Replace 'CMSIS Device' and 'HAL Driver' folders by submodules 2023-10-31 14:13:29 +01:00
Rania JMAI 5326afcfb2 Release v1.8.5 2023-04-28 10:02:38 +01:00
Denys Fedoryshchenko 756b239424 startup_stm32f100xb.s: Small typo fix for SPI1_IRQHandler
Fixes small typo that cause lot of confusion for users using CMSIS.

Signed-off-by: Denys Fedoryshchenko <denys.f@collabora.com>
2023-04-06 11:32:37 +01:00
deividAlfa 218b5100dd Declare DMA Handler State as volatile
Not doing so causes issues when optimizations are enabled, the flag can change at any time by the DMA interrupt, but the compiler is unaware.
2022-04-19 15:11:54 +01:00
Eya c750eab699 Release v1.8.4 2021-06-07 17:37:27 +01:00
Maerdl 0813c2c1a3 wrong define used to clear I2C ADDR flag 2021-05-12 15:46:34 +01:00
Attie Grande f5aaa9b454 Add support for running SYSCLK from PLL1, via PLL2.
For parts like the STM32F1 Connectivity Line (STM32F105xx, STM32F107xx),
it is occasionally necessary to source SYSCLK via PLL2. This patch will
add this support.

- Add: `UTILS_GetPLL2OutputFrequency()` to calculate the output frequency of PLL2
- Add: `LL_PLL_ConfigSystemClock_PLL2()` to configure the system clock as sourced from HSE, via PLL2 and PLL1.
- Add: Miscellaneous support definitions.

Signed-off-by: Attie Grande <attie.grande@argentum-systems.co.uk>
2021-04-05 14:25:41 +01:00
Eya 276c4ab953 Release v1.8.3 2020-10-30 15:10:41 +01:00
rihab kouki 003dfc9e6c Release v1.8.2 2020-10-05 08:36:58 +01:00
Eya 6ead386a08 Release v1.8.1 2020-08-28 17:16:38 +01:00
Eya 441b2cbdc2 Release v1.8.0 2019-07-19 14:54:54 +01:00