314 lines
11 KiB
C
314 lines
11 KiB
C
/**
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******************************************************************************
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* @file system_stm32f0xx.c
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* @author MCD Application Team
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* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
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*
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* 1. This file provides two functions and one global variable to be called from
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* user application:
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* - SystemInit(): This function is called at startup just after reset and
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* before branch to main program. This call is made inside
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* the "startup_stm32f0xx.s" file.
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*
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* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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* by the user application to setup the SysTick
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* timer or configure other parameters.
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*
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* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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* be called whenever the core clock is changed
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* during program execution.
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*
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* 2. After each device reset the HSI (8 MHz) is used as system clock source.
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* Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
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* configure the system clock before to branch to main program.
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*
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* 3. This file configures the system clock as follows:
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*=============================================================================
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* Supported STM32F0xx device
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*-----------------------------------------------------------------------------
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* System Clock source | HSI
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*-----------------------------------------------------------------------------
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* SYSCLK(Hz) | 8000000
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*-----------------------------------------------------------------------------
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* HCLK(Hz) | 8000000
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*-----------------------------------------------------------------------------
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* AHB Prescaler | 1
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*-----------------------------------------------------------------------------
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* APB1 Prescaler | 1
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*-----------------------------------------------------------------------------
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*=============================================================================
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32f0xx_system
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* @{
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*/
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/** @addtogroup STM32F0xx_System_Private_Includes
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* @{
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*/
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#include "stm32f0xx.h"
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/**
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* @}
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*/
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/** @addtogroup STM32F0xx_System_Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32F0xx_System_Private_Defines
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* @{
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*/
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#if !defined (HSE_VALUE)
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#define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
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This value can be provided and adapted by the user application. */
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#endif /* HSE_VALUE */
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#if !defined (HSI_VALUE)
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#define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
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This value can be provided and adapted by the user application. */
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#endif /* HSI_VALUE */
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#if !defined (HSI48_VALUE)
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#define HSI48_VALUE ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in Hz.
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This value can be provided and adapted by the user application. */
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#endif /* HSI48_VALUE */
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/**
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* @}
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*/
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/** @addtogroup STM32F0xx_System_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32F0xx_System_Private_Variables
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* @{
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*/
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/* This variable is updated in three ways:
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1) by calling CMSIS function SystemCoreClockUpdate()
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2) by calling HAL API function HAL_RCC_GetHCLKFreq()
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3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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Note: If you use this function to configure the system clock there is no need to
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call the 2 first functions listed above, since SystemCoreClock variable is
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updated automatically.
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*/
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uint32_t SystemCoreClock = 8000000;
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const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
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/**
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* @}
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*/
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/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32F0xx_System_Private_Functions
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* @{
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*/
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/**
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* @brief Setup the microcontroller system.
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* Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
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* @param None
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* @retval None
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*/
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void SystemInit(void)
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{
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/* Reset the RCC clock configuration to the default reset state ------------*/
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/* Set HSION bit */
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RCC->CR |= (uint32_t)0x00000001U;
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#if defined (STM32F051x8) || defined (STM32F058x8)
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/* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
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RCC->CFGR &= (uint32_t)0xF8FFB80CU;
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#else
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/* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
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RCC->CFGR &= (uint32_t)0x08FFB80CU;
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#endif /* STM32F051x8 or STM32F058x8 */
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/* Reset HSEON, CSSON and PLLON bits */
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RCC->CR &= (uint32_t)0xFEF6FFFFU;
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/* Reset HSEBYP bit */
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RCC->CR &= (uint32_t)0xFFFBFFFFU;
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/* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
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RCC->CFGR &= (uint32_t)0xFFC0FFFFU;
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/* Reset PREDIV[3:0] bits */
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RCC->CFGR2 &= (uint32_t)0xFFFFFFF0U;
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#if defined (STM32F072xB) || defined (STM32F078xx)
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/* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU;
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#elif defined (STM32F071xB)
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/* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFFFCEACU;
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#elif defined (STM32F091xC) || defined (STM32F098xx)
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/* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFF0FEACU;
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#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
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/* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFFFFEECU;
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#elif defined (STM32F051x8) || defined (STM32F058xx)
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/* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFFFFEACU;
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#elif defined (STM32F042x6) || defined (STM32F048xx)
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/* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFFFFE2CU;
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#elif defined (STM32F070x6) || defined (STM32F070xB)
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/* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
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RCC->CFGR3 &= (uint32_t)0xFFFFFE6CU;
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/* Set default USB clock to PLLCLK, since there is no HSI48 */
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RCC->CFGR3 |= (uint32_t)0x00000080U;
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#else
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#warning "No target selected"
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#endif
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/* Reset HSI14 bit */
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RCC->CR2 &= (uint32_t)0xFFFFFFFEU;
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/* Disable all interrupts */
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RCC->CIR = 0x00000000U;
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}
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/**
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* @brief Update SystemCoreClock variable according to Clock Register Values.
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* The SystemCoreClock variable contains the core clock (HCLK), it can
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* be used by the user application to setup the SysTick timer or configure
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* other parameters.
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*
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* @note Each time the core clock (HCLK) changes, this function must be called
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* to update SystemCoreClock variable value. Otherwise, any configuration
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* based on this variable will be incorrect.
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*
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* @note - The system frequency computed by this function is not the real
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* frequency in the chip. It is calculated based on the predefined
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* constant and the selected clock source:
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*
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* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
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*
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* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
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*
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* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
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* or HSI_VALUE(*) multiplied/divided by the PLL factors.
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*
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* (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
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* 8 MHz) but the real value may vary depending on the variations
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* in voltage and temperature.
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*
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* (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
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* 8 MHz), user has to ensure that HSE_VALUE is same as the real
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* frequency of the crystal used. Otherwise, this function may
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* have wrong result.
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*
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* - The result of this function could be not correct when using fractional
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* value for HSE crystal.
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*
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* @param None
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* @retval None
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*/
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void SystemCoreClockUpdate (void)
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{
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uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
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/* Get SYSCLK source -------------------------------------------------------*/
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tmp = RCC->CFGR & RCC_CFGR_SWS;
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switch (tmp)
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{
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case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
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SystemCoreClock = HSI_VALUE;
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break;
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case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
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SystemCoreClock = HSE_VALUE;
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break;
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case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
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/* Get PLL clock source and multiplication factor ----------------------*/
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pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
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pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
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pllmull = ( pllmull >> 18) + 2;
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predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
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if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
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{
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/* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
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SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
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}
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#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
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else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
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{
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/* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
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SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
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}
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#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
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else
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{
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#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \
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|| defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \
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|| defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
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/* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
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SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
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#else
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/* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
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SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
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#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
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STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
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STM32F091xC || STM32F098xx || STM32F030xC */
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}
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break;
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default: /* HSI used as system clock */
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SystemCoreClock = HSI_VALUE;
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break;
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}
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/* Compute HCLK clock frequency ----------------*/
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/* Get HCLK prescaler */
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tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
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/* HCLK clock frequency */
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SystemCoreClock >>= tmp;
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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