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增加资料连接. 

Signed-off-by: rick.chan <cy187lion@sina.com>
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rick.chan 2023-12-19 09:12:21 +08:00
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17
Hardware/Theory/PCB_差分布线.md
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@ -16,11 +16,12 @@ TODO:
## 外部参考资料 ## 外部参考资料
1. [PCB上形式多种多样的差分线对，平衡+等长的原则是一样的](https://www.bilibili.com/video/BV19z4y1J7gH/?spm_id_from=333.788&vd_source=39828f775e4351350ea464b48d3a004b) 1. [Nightly Build](https://downloads.kicad.org/kicad/windows/explore/nightlies)
2. [差分线设计要点](https://www.bilibili.com/video/BV1o14y1d77N/?spm_id_from=333.788.recommend_more_video.2&vd_source=39828f775e4351350ea464b48d3a004b) 2. [PCB上形式多种多样的差分线对，平衡+等长的原则是一样的](https://www.bilibili.com/video/BV19z4y1J7gH/?spm_id_from=333.788&vd_source=39828f775e4351350ea464b48d3a004b)
3. [遇到两层板走差分线，我是这样做阻抗匹配设计和等长设计](https://baijiahao.baidu.com/s?id=1705860164618608422&wfr=spider&for=pc) 3. [差分线设计要点](https://www.bilibili.com/video/BV1o14y1d77N/?spm_id_from=333.788.recommend_more_video.2&vd_source=39828f775e4351350ea464b48d3a004b)
4. [双面板SOC系统硬件开发设计概要](https://www.icspec.com/news/article-details/2179773) 4. [遇到两层板走差分线，我是这样做阻抗匹配设计和等长设计](https://baijiahao.baidu.com/s?id=1705860164618608422&wfr=spider&for=pc)
5. [嘉立创技术指导：阻抗设计说明](https://www.jlc.com/portal/server_guide_38565.html) 5. [双面板SOC系统硬件开发设计概要](https://www.icspec.com/news/article-details/2179773)
6. [嘉立创层压结构](https://tools.jlc.com/jlcTools/#/impedanceDefaultTemplate) 6. [嘉立创技术指导：阻抗设计说明](https://www.jlc.com/portal/server_guide_38565.html)
7. [嘉立创阻抗计算神器](https://tools.jlc.com/jlcTools/index.html#/impedanceCalculatenew) 7. [嘉立创层压结构](https://tools.jlc.com/jlcTools/#/impedanceDefaultTemplate)
8. [PCB 传输线教程（上）：基于 Polar Si9000 与嘉立创工艺的传输线设计](https://blog.csdn.net/Surrea1/article/details/130325719) 8. [嘉立创阻抗计算神器](https://tools.jlc.com/jlcTools/index.html#/impedanceCalculatenew)
9. [PCB 传输线教程（上）：基于 Polar Si9000 与嘉立创工艺的传输线设计](https://blog.csdn.net/Surrea1/article/details/130325719)