475 lines
29 KiB
C
475 lines
29 KiB
C
/****************************************************************************
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* include/nuttx/net/mii.h
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*
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* Copyright (C) 2008-2010, 2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __INCLUDE_NUTTX_NET_MII_H
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#define __INCLUDE_NUTTX_NET_MII_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-Processor Definitions
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****************************************************************************/
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/* MII register offsets *****************************************************/
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/* Common MII management registers. The IEEE 802.3 standard specifies a
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* register set for controlling and gathering status from the PHY layer. The
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* registers are collectively known as the MII Management registers and are
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* detailed in Section 22.2.4 of the IEEE 802.3 specification.
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*/
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#define MII_MCR 0x00 /* MII management control */
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#define MII_MSR 0x01 /* MII management status */
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#define MII_PHYID1 0x02 /* PHY ID 1 */
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#define MII_PHYID2 0x03 /* PHY ID 2 */
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#define MII_ADVERTISE 0x04 /* Auto-negotiation advertisement */
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#define MII_LPA 0x05 /* Auto-negotiation link partner base page ability */
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#define MII_EXPANSION 0x06 /* Auto-negotiation expansion */
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#define MII_NEXTPAGE 0x07 /* Auto-negotiation next page */
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#define MII_LPANEXTPAGE 0x08 /* Auto-negotiation link partner received next page */
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#define MII_MSCONTROL 0x09 /* Master/slave control register */
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#define MII_MSSTATUS 0x0a /* Master/slave status register */
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#define MII_PSECONTROL 0x0b /* PSE control register */
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#define MII_PSESTATUS 0x0c /* PSE status register */
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#define MII_MMDCONTROL 0x0d /* MMD access control register */
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#define MII_ESTATUS 0x0f /* Extended status register */
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/* Extended Registers: Registers 16-31 may be used for vendor specific abilities */
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/* National Semiconductor DP83840: 0x07-0x11, 0x14, 0x1a, 0x1d-0x1f reserved */
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#define MII_DP83840_COUNTER 0x12 /* Disconnect counter */
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#define MII_DP83840_FCSCOUNTER 0x13 /* False carrier sense counter */
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#define MII_DP83840_NWAYTEST 0x14 /* N-way auto-neg test reg */
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#define MII_DP83840_RERRCOUNTER 0x15 /* Receive error counter */
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#define MII_DP83840_SREVISION 0x16 /* Silicon revision */
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#define MII_DP83840_LBRERROR 0x18 /* Loopback, bypass and receiver error */
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#define MII_DP83840_PHYADDR 0x19 /* PHY address */
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#define MII_DP83840_10BTSR 0x1b /* 10BASE-T status register */
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#define MII_DP83840_10BTCR 0x1c /* 10BASE-T configuration register */
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/* National Semiconductor DP83848C: 0x8-0x15, 0x13, 0x1c reserved */
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#define MII_DP83848C_PHYSTS 0x10 /* RO PHY Status Register */
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#define MII_DP83848C_MICR 0x11 /* RW MII Interrupt Control Register */
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#define MII_DP83848C_MISR 0x12 /* RO MII Interrupt Status Register */
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#define MII_DP83848C_FCSCR 0x14 /* RO False Carrier Sense Counter Register */
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#define MII_DP83848C_RECR 0x15 /* RO Receive Error Counter Register */
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#define MII_DP83848C_PCSR 0x16 /* RW PCS Sub-Layer Configuration and Status Register */
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#define MII_DP83848C_RBR 0x17 /* RW RMII and Bypass Register */
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#define MII_DP83848C_LEDCR 0x18 /* RW LED Direct Control Register */
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#define MII_DP83848C_PHYCR 0x19 /* RW PHY Control Register */
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#define MII_DP83848C_10BTSCR 0x1a /* RW 10Base-T Status/Control Register */
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#define MII_DP83848C_CDCTRL1 0x1b /* RW CD Test Control Register and BIST Extensions Register */
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#define MII_DP83848C_EDCR 0x1e /* RW Energy Detect */
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/* Am79c874: 0x08-0x0f, 0x14, 0x16, 0x19-0x1f reserved */
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#define MII_AM79C874_NPADVERTISE 0x07 /* Auto-negotiation next page advertisement */
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#define MII_AM79C874_MISCFEATURES 0x10 /* Miscellaneous features reg */
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#define MII_AM79C874_INTCS 0x11 /* Interrupt control/status */
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#define MII_AM79C874_DIAGNOSTIC 0x12 /* Diagnostic */
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#define MII_AM79C874_LOOPBACK 0x13 /* Power management/loopback */
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#define MII_AM79C874_MODEC 0x15 /* Mode control register */
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#define MII_AM79C874_DISCONNECT 0x17 /* Disconnect counter */
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#define MII_AM79C874_RCVERROR 0x18 /* Receive error counter */
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/* Luminary LM3S6918 built-in PHY: 0x07-0x0f, 0x14-0x16, 0x19-0x1f reserved */
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#define MII_LM3S_VSPECIFIC 0x10 /* Vendor-Specific */
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#define MII_LM3S_INTCS 0x11 /* Interrupt control/status */
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#define MII_LM3S_DIAGNOSTIC 0x12 /* Diagnostic */
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#define MII_LM3S_XCVRCONTROL 0x13 /* Transceiver Control */
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#define MII_LM3S_LEDCONFIG 0x17 /* LED Configuration */
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#define MII_LM3S_MDICONTROL 0x18 /* Ethernet PHY Management MDI/MDIX Control */
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/* Micrel KS8721: 0x15, 0x1b, and 0x1f */
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#define MII_KS8721_RXERCOUNTER 0x15 /* RXER counter */
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#define MII_KS8721_INTCS 0x1b /* Interrupt control/status register */
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#define MII_KS8721_10BTCR 0x1f /* 10BASE-TX PHY control register */
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/* National Semiconductor DP83848C PHY Extended Registers */
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#define MII_DP83848C_STS 0x10 /* Status Register */
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#define MII_DP83848C_MICR 0x11 /* MII Interrupt Control Register */
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#define MII_DP83848C_MISR 0x12 /* MII Interrupt Status Register */
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#define MII_DP83848C_FCSCR 0x14 /* False Carrier Sense Counter */
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#define MII_DP83848C_RECR 0x15 /* Receive Error Counter */
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#define MII_DP83848C_PCSR 0x16 /* PCS Sublayer Config. and Status */
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#define MII_DP83848C_RBR 0x17 /* RMII and Bypass Register */
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#define MII_DP83848C_LEDCR 0x18 /* LED Direct Control Register */
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#define MII_DP83848C_PHYCR 0x19 /* PHY Control Register */
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#define MII_DP83848C_10BTSCR 0x1a /* 10Base-T Status/Control Register */
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#define MII_DP83848C_CDCTRL1 0x1b /* CD Test Control and BIST Extens */
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#define MII_DP83848C_EDCR 0x1d /* Energy Detect Control Register */
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/* SMSC LAN8720 PHY Extended Registers */
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#define MII_LAN8720_REV 0x10 /* Silicon Revision Register */
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#define MII_LAN8720_MCSR 0x11 /* Mode Control/Status Register */
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#define MII_LAN8720_MODES 0x12 /* Special modes */
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#define MII_LAN8720_SECR 0x1a /* Symbol Error Counter Register */
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#define MII_LAN8720_CSIR 0x1b /* Control / Status Indicator Register */
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#define MII_LAN8720_SITC 0x1c /* Special Internal Testability Controls */
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#define MII_LAN8720_ISR 0x1d /* Interrupt Source Register */
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#define MII_LAN8720_IMR 0x1e /* Interrupt Mask Register */
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#define MII_LAN8720_SCSR 0x1f /* PHY Special Control/Status Register */
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/* GMII */
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#define GMII_MCR MII_MCR /* GMII management control */
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#define GMII_MSR MII_MSR /* GMII management status */
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#define GMII_PHYID1 MII_PHYID1 /* PHY ID 1 */
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#define GMII_PHYID2 MII_PHYID2 /* PHY ID 2 */
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#define GMII_ADVERTISE MII_ADVERTISE /* Auto-negotiation advertisement */
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#define GMII_LPA MII_LPA /* Auto-negotiation link partner base page ability */
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#define GMII_EXPANSION MII_EXPANSION /* Auto-negotiation expansion */
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#define GMII_NEXTPAGE MII_NEXTPAGE /* Auto-negotiation next page */
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#define GMII_LPANEXTPAGE MII_LPANEXTPAGE /* Auto-negotiation link partner received next page */
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#define GMII_CTRL1000 0x09 /* 1000BASE-T control */
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#define GMII_STAT1000 0x0a /* 1000BASE-T status */
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#define GMII_ESTATUS MII_ESTATUS /* Extended status register */
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/* MII register bit settings ************************************************/
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/* MII Control register bit definitions */
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#define MII_MCR_UNIDIR (1 << 5) /* Bit 5: Unidirectional enable */
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#define MII_MCR_SPEED1000 (1 << 6) /* Bit 6: MSB of Speed (1000 reserved on 10/100) */
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#define MII_MCR_CTST (1 << 7) /* Bit 7: Enable collision test */
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#define MII_MCR_FULLDPLX (1 << 8) /* Bit 8: Full duplex */
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#define MII_MCR_ANRESTART (1 << 9) /* Bit 9: Restart auto negotiation */
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#define MII_MCR_ISOLATE (1 << 10) /* Bit 10: Electronically isolate PHY from MII */
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#define MII_MCR_PDOWN (1 << 11) /* Bit 11: Powerdown the PHY */
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#define MII_MCR_ANENABLE (1 << 12) /* Bit 12: Enable auto negotiation */
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#define MII_MCR_SPEED100 (1 << 13) /* Bit 13: Select 100Mbps */
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#define MII_MCR_LOOPBACK (1 << 14) /* Bit 14: Enable loopback mode */
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#define MII_MCR_RESET (1 << 15) /* Bit 15: PHY reset */
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/* MII Status register bit definitions */
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#define MII_MSR_EXTCAP (1 << 0) /* Bit 0: Extended register capability */
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#define MII_MSR_JABBERDETECT (1 << 1) /* Bit 1: Jabber detect */
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#define MII_MSR_LINKSTATUS (1 << 2) /* Bit 2: Link status */
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#define MII_MSR_ANEGABLE (1 << 3) /* Bit 3: Auto-negotiation able */
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#define MII_MSR_RFAULT (1 << 4) /* Bit 4: Remote fault */
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#define MII_MSR_ANEGCOMPLETE (1 << 5) /* Bit 5: Auto-negotiation complete */
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#define MII_MSR_MFRAMESUPPRESS (1 << 6) /* Bit 6: Management frame suppression */
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#define MII_MSR_ESTATEN (1 << 8) /* Bit 8: Extended Status in R15 */
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#define MII_MSR_100BASET2FULL (1 << 9) /* Bit 9: 100BASE-T2 half duplex able */
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#define MII_MSR_100BASET2HALF (1 << 10) /* Bit 10: 100BASE-T2 full duplex able */
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#define MII_MSR_10BASETXHALF (1 << 11) /* Bit 11: 10BASE-TX half duplex able */
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#define MII_MSR_10BASETXFULL (1 << 12) /* Bit 12: 10BASE-TX full duplex able */
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#define MII_MSR_100BASETXHALF (1 << 13) /* Bit 13: 100BASE-TX half duplex able */
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#define MII_MSR_100BASETXFULL (1 << 14) /* Bit 14: 100BASE-TX full duplex able */
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#define MII_MSR_100BASET4 (1 << 15) /* Bit 15: 100BASE-T4 able */
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/* MII ID2 register bits */
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#define MII_PHYID2_OUI 0xfc00 /* Bits 19-24 of OUI mask */
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#define MII_PHYID2_MODEL 0x03f0 /* Model number mask */
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#define MII_PHYID2_REV 0x000f /* Revision number mask */
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/* Advertisement control register bit definitions */
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#define MII_ADVERTISE_SELECT 0x001f /* Bits 0-4: Selector field */
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#define MII_ADVERTISE_CSMA (1 << 0) /* CSMA */
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#define MII_ADVERTISE_8023 (1 << 0) /* IEEE Std 802.3 */
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#define MII_ADVERTISE_8029 (2 << 0) /* IEEE Std 802.9 ISLAN-16T */
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#define MII_ADVERTISE_8025 (3 << 0) /* IEEE Std 802.5 */
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#define MII_ADVERTISE_1394 (4 << 0) /* IEEE Std 1394 */
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#define MII_ADVERTISE_10BASETXHALF (1 << 5) /* Bit 5: Try 10BASE-TX half duplex */
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#define MII_ADVERTISE_1000XFULL (1 << 5) /* Bit 5: Try 1000BASE-X full duplex */
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#define MII_ADVERTISE_10BASETXFULL (1 << 6) /* Bit 6: Try 10BASE-TX full duplex */
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#define MII_ADVERTISE_1000XHALF (1 << 6) /* Bit 6: Try 1000BASE-X half duplex */
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#define MII_ADVERTISE_100BASETXHALF (1 << 7) /* Bit 7: Try 100BASE-TX half duplex */
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#define MII_ADVERTISE_1000XPAUSE (1 << 7) /* Bit 7: Try 1000BASE-X pause */
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#define MII_ADVERTISE_100BASETXFULL (1 << 8) /* Bit 8: Try 100BASE-TX full duplex*/
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#define MII_ADVERTISE_1000XASYMPAU (1 << 8) /* Bit 8: Try 1000BASE-X asym pause */
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#define MII_ADVERTISE_100BASET4 (1 << 9) /* Bit 9: Try 100BASE-T4 */
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#define MII_ADVERTISE_FDXPAUSE (1 << 10) /* Bit 10: Try full duplex flow control */
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#define MII_ADVERTISE_ASYMPAUSE (1 << 11) /* Bit 11: Try asymetric pause */
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#define MII_ADVERTISE_RFAULT (1 << 13) /* Bit 13: Remote fault supported */
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#define MII_ADVERTISE_LPACK (1 << 14) /* Bit 14: Ack link partners response */
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#define MII_ADVERTISE_NXTPAGE (1 << 15) /* Bit 15: Next page enabled */
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/* Link partner ability register bit definitions */
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#define MII_LPA_SELECT 0x001f /* Bits 0-4: Link partner selector field */
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#define MII_LPA_CSMA (1 << 0) /* CSMA */
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#define MII_LPA_8023 (1 << 0) /* IEEE Std 802.3 */
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#define MII_LPA_8029 (2 << 0) /* IEEE Std 802.9 ISLAN-16T */
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#define MII_LPA_8025 (3 << 0) /* IEEE Std 802.5 */
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#define MII_LPA_1394 (4 << 0) /* IEEE Std 1394 */
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#define MII_LPA_10BASETXHALF (1 << 5) /* Bit 5: 10BASE-TX half duplex able */
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#define MII_LPA_1000XFULL (1 << 5) /* Bit 5: 1000BASE-X full-duplex able */
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#define MII_LPA_10BASETXFULL (1 << 6) /* Bit 6: 10BASE-TX full duplex able */
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#define MII_LPA_1000XHALF (1 << 6) /* Bit 6: 1000BASE-X half-duplex */
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#define MII_LPA_100BASETXHALF (1 << 7) /* Bit 7: 100BASE-TX half duplex able */
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#define MII_LPA_1000XPAUSE (1 << 7) /* Bit 7: 1000BASE-X pause able */
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#define MII_LPA_100BASETXFULL (1 << 8) /* Bit 8: 100BASE-TX full duplex able */
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#define MII_LPA_1000XASYMPAU (1 << 8) /* Bit 8: 1000BASE-X asym pause able */
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#define MII_LPA_100BASET4 (1 << 9) /* Bit 9: 100BASE-T4 able */
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#define MII_LPA_FDXPAUSE (1 << 10) /* Bit 10: Full duplex flow control able */
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#define MII_LPA_ASYMPAUSE (1 << 11) /* Bit 11: Asynchronous pause able */
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#define MII_LPA_RFAULT (1 << 13) /* Bit 13: Link partner remote fault request */
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#define MII_LPA_LPACK (1 << 14) /* Bit 14: Link partner acknowledgement */
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#define MII_LPA_NXTPAGE (1 << 15) /* Bit 15: Next page requested */
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/* Link partner ability in next page format */
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#define MII_LPANP_MESSAGE 0x07ff /* Bits 0-10: Link partner's message code */
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#define MII_LPANP_TOGGLE (1 << 11) /* Bit 11: Link partner toggle */
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#define MII_LPANP_LACK2 (1 << 12) /* Bit 12: Link partner can comply ACK */
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#define MII_LPANP_MSGPAGE (1 << 13) /* Bit 13: Link partner message page request */
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#define MII_LPANP_LPACK (1 << 14) /* Bit 14: Link partner acknowledgement */
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#define MII_LPANP_NXTPAGE (1 << 15) /* Bit 15: Next page requested */
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/* MII Auto-negotiation expansion register bit definitions */
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#define MII_EXPANSION_ANEGABLE (1 << 0) /* Bit 0: Link partner is auto-negotion able */
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#define MII_EXPANSION_PAGERECVD (1 << 1) /* Bit 1: New link code word in LPA ability reg */
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#define MII_EXPANSION_ENABLENPAGE (1 << 2) /* Bit 2: This enables npage words */
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#define MII_EXPANSION_NXTPAGEABLE (1 << 3) /* Bit 3: Link partner supports next page */
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#define MII_EXPANSION_PARFAULTS (1 << 4) /* Bit 4: Fault detected by parallel logic */
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/* Auto-negotiation next page advertisement */
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#define MII_NPADVERTISE_CODE 0x07ff /* Bits 0-10: message/un-formated code field */
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#define MII_NPADVERTISE_TOGGLE (1 << 11) /* Bit 11: Toggle */
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#define MII_NPADVERTISE_ACK2 (1 << 12) /* Bit 12: Acknowledgement 2 */
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#define MII_NPADVERTISE_MSGPAGE (1 << 13) /* Bit 13: Message page */
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#define MII_NPADVERTISE_NXTPAGE (1 << 15) /* Bit 15: Next page indication */
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/* MII PHYADDR register bit definitions */
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#define DP83840_PHYADDR_DUPLEX (1 << 7)
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#define DP83840_PHYADDR_SPEED (1 << 6)
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/* National Semiconductor DP83848C ******************************************/
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/* DP83848C MII ID1/2 register bits */
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#define MII_PHYID1_DP83848C 0x2000 /* ID1 value for DP83848C */
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#define MII_PHYID2_DP83848C 0x5c90 /* ID2 value for DP83848C */
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/* RMII and Bypass Register (0x17) */
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#define MII_RBR_ELAST_MASK 0x0003 /* Bits 0-1: Receive elasticity buffer */
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# define MII_RBR_ELAST_14 0x0000 /* 14 bit tolerance */
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# define MII_RBR_ELAST_2 0x0001 /* 2 bit tolerance */
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# define MII_RBR_ELAST_6 0x0002 /* 6 bit tolerance */
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# define MII_RBR_ELAST_10 0x0003 /* 10 bit tolerance */
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#define MII_RBR_RXUNFSTS (1 << 2) /* Bit 2: RX FIFO underflow */
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#define MII_RBR_RXOVFSTS (1 << 3) /* Bit 3: RX FIFO overflow */
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#define MII_RBR_RMIIREV10 (1 << 4) /* Bit 4: 0=RMIIv1.2 1-RMIIv1.0 */
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#define MII_RBR_RMIIMODE (1 << 5) /* Bit 5: 0=MII mode 1=RMII mode */
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/* SMSC LAN8720 *************************************************************/
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/* SMSC LAN8720 MII ID1/2 register bits */
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#define MII_PHYID1_LAN8720 0x0007 /* ID1 value for LAN8720 */
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#define MII_PHYID2_LAN8720 0xc0f1 /* ID2 value for LAN8720 */
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/* Am79c874-specific register bit settings **********************************/
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/* Am79c874 MII ID1/2 register bits */
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#define MII_PHYID1_AM79C874 0x0022 /* ID1 value for Am79c874 */
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#define MII_PHYID2_AM79C874 0x561b /* ID2 value for Am79c874 Rev B */
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/* Am79c874 diagnostics register */
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#define AM79C874_DIAG_RXLOCK (1 << 8) /* Bit 8: 1=Rcv PLL locked on */
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#define AM79C874_DIAG_RXPASS (1 << 9) /* Bit 9: 1=Operating in 100Base-X mode */
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#define AM79C874_DIAG_100MBPS (1 << 10) /* Bit 10: 1=ANEG result is 100Mbps */
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#define AM79C874_DIAG_FULLDPLX (1 << 11) /* Bit 11: 1=ANEG result is full duplex */
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/* LM3S6918-specific register bit settings **********************************/
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/* LM3S6918 Vendor-Specific, address 0x10 */
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#define LM3S_VSPECIFIC_RXCC (1 << 0) /* Bit 0: Receive Clock Control*/
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#define LM3S_VSPECIFIC_PCSBP (1 << 1) /* Bit 1: PCS Bypass */
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#define LM3S_VSPECIFIC_RVSPOL (1 << 4) /* Bit 4: Receive Data Polarity */
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#define LM3S_VSPECIFIC_APOL (1 << 5) /* Bit 5: Auto-Polarity Disable */
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#define LM3S_VSPECIFIC_NL10 (1 << 10) /* Bit 10: Natural Loopback Mode */
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#define LM3S_VSPECIFIC_SQEI (1 << 11) /* Bit 11: SQE Inhibit Testing */
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#define LM3S_VSPECIFIC_TXHIM (1 << 12) /* Bit 12: Transmit High Impedance Mode */
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#define LM3S_VSPECIFIC_INPOL (1 << 14) /* Bit 14: Interrupt Polarity Value*/
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#define LM3S_VSPECIFIC_RPTR (1 << 15) /* Bit 15: Repeater mode*/
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/* LM3S6918 Interrupt Control/Status, address 0x11 */
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#define LM3S_INTCS_ANEGCOMPINT (1 << 0) /* Bit 0: Auto-Negotiation Complete Interrupt */
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#define LM3S_INTCS_RFAULTINT (1 << 1) /* Bit 1: Remote Fault Interrupt */
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#define LM3S_INTCS_LSCHGINT (1 << 2) /* Bit 2: Link Status Change Interrupt */
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#define LM3S_INTCS_LPACKINT (1 << 3) /* Bit 3: LP Acknowledge Interrupt */
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#define LM3S_INTCS_PDFINT (1 << 4) /* Bit 4: Parallel Detection Fault Interrupt */
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#define LM3S_INTCS_PRXINT (1 << 5) /* Bit 5: Page Receive Interrupt */
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#define LM3S_INTCS_RXERINT (1 << 6) /* Bit 6: Receive Error Interrupt */
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#define LM3S_INTCS_JABBERINT (1 << 7) /* Bit 7: Jabber Event Interrupt */
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#define LM3S_INTCS_ANEGCOMPIE (1 << 8) /* Bit 8: Auto-Negotiation Complete Interrupt Enable */
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#define LM3S_INTCS_RFAULTIE (1 << 9) /* Bit 9: Remote Fault Interrupt Enable */
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#define LM3S_INTCS_LSCHGIE (1 << 10) /* Bit 10: Link Status Change Interrupt Enable */
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#define LM3S_INTCS_LPACKIE (1 << 11) /* Bit 11: LP Acknowledge Interrupt Enable */
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#define LM3S_INTCS_PDFIE (1 << 12) /* Bit 12: Parallel Detection Fault Interrupt Enable */
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#define LM3S_INTCS_PRXIE (1 << 13) /* Bit 13: Page Received Interrupt Enable */
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#define LM3S_INTCS_RXERIE (1 << 14) /* Bit 14: Receive Error Interrupt Enable */
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#define LM3S_INTCS_JABBERIE (1 << 15) /* Bit 15: Jabber Interrupt Enable */
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/* LM3S6918 Diagnostic, address 0x12 */
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#define LM3S_DIAGNOSTIC_RX_LOCK (1 << 8) /* Bit 8: Receive PLL Lock */
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#define LM3S_DIAGNOSTIC_RXSD (1 << 9) /* Bit 9: Receive Detection */
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#define LM3S_DIAGNOSTIC_RATE (1 << 10) /* Bit 10: Rate */
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#define LM3S_DIAGNOSTIC_DPLX (1 << 11) /* Bit 11: Duplex Mode */
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#define LM3S_DIAGNOSTIC_ANEGF (1 << 12) /* Bit 12: Auto-Negotiation Failure */
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/* LM3S6918 Transceiver Control, address 0x13 */
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#define LM3S_XCVRCONTROL_TXO_SHIFT 14 /* Bits 15-14: Transmit Amplitude Selection */
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#define LM3S_XCVRCONTROL_TXO_MASK (3 << LM3S_XCVRCONTROL_TXO_SHIFT)
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#define LM3S_XCVRCONTROL_TXO_00DB (0 << LM3S_XCVRCONTROL_TXO_SHIFT) /* Gain 0.0dB of insertion loss */
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#define LM3S_XCVRCONTROL_TXO_04DB (1 << LM3S_XCVRCONTROL_TXO_SHIFT) /* Gain 0.4dB of insertion loss */
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#define LM3S_XCVRCONTROL_TXO_08DB (2 << LM3S_XCVRCONTROL_TXO_SHIFT) /* Gain 0.8dB of insertion loss */
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#define LM3S_XCVRCONTROL_TXO_12DB (3 << LM3S_XCVRCONTROL_TXO_SHIFT) /* Gain 1.2dB of insertion loss */
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/* LM3S6918 LED Configuration, address 0x17 */
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#define LM3S_LEDCONFIG_LED0_SHIFT (0) /* Bits 3-0: LED0 Source */
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#define LM3S_LEDCONFIG_LED0_MASK (0x0f << LM3S_LEDCONFIG_LED0_SHIFT)
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#define LM3S_LEDCONFIG_LED0_LINKOK (0 << LM3S_LEDCONFIG_LED0_SHIFT) /* Link OK */
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#define LM3S_LEDCONFIG_LED0_RXTX (1 << LM3S_LEDCONFIG_LED0_SHIFT) /* RX or TX activity */
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#define LM3S_LEDCONFIG_LED0_100BASET (5 << LM3S_LEDCONFIG_LED0_SHIFT) /* 100BASE-TX mode */
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#define LM3S_LEDCONFIG_LED0_10BASET (6 << LM3S_LEDCONFIG_LED0_SHIFT) /* 10BASE-T mode */
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#define LM3S_LEDCONFIG_LED0_FDUPLEX (7 << LM3S_LEDCONFIG_LED0_SHIFT) /* Full duplex */
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#define LM3S_LEDCONFIG_LED0_OKRXTX (8 << LM3S_LEDCONFIG_LED0_SHIFT) /* Full duplex */
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#define LM3S_LEDCONFIG_LED1_SHIFT (4) /* Bits 7-4: LED1 Source */
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#define LM3S_LEDCONFIG_LED1_MASK (0x0f << LM3S_LEDCONFIG_LED1_SHIFT)
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#define LM3S_LEDCONFIG_LED1_LINKOK (0 << LM3S_LEDCONFIG_LED1_SHIFT) /* Link OK */
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#define LM3S_LEDCONFIG_LED1_RXTX (1 << LM3S_LEDCONFIG_LED1_SHIFT) /* RX or TX activity */
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#define LM3S_LEDCONFIG_LED1_100BASET (5 << LM3S_LEDCONFIG_LED1_SHIFT) /* 100BASE-TX mode */
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#define LM3S_LEDCONFIG_LED1_10BASET (6 << LM3S_LEDCONFIG_LED1_SHIFT) /* 10BASE-T mode */
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#define LM3S_LEDCONFIG_LED1_FDUPLEX (7 << LM3S_LEDCONFIG_LED1_SHIFT) /* Full duplex */
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#define LM3S_LEDCONFIG_LED1_OKRXTX (8 << LM3S_LEDCONFIG_LED1_SHIFT) /* Full duplex */
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/* LM3S6918 MDI/MDIX Control, address 0x18 */
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#define LM3S_MDICONTROL_MDIXSD_SHIFT (0) /* Bits 3-0: Auto-Switching Seed */
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#define LM3S_MDICONTROL_MDIXSD_MASK (0x0f << LM3S_MDICONTROL_MDIXSD_SHIFT)
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#define LM3S_MDICONTROL_MDIXCM (1 << 4) /* Bit 4: Auto-Switching Complete */
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#define LM3S_MDICONTROL_MDIX (1 << 5) /* Bit 5: Auto-Switching Configuration */
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#define LM3S_MDICONTROL_AUTOSW (1 << 6) /* Bit 6: Auto-Switching Enable */
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#define LM3S_MDICONTROL_PDMODE (1 << 7) /* Bit 7: Parallel Detection Mode */
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/* KS8921-specific register bit settings ************************************/
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/* KS8921 MII Control register bit definitions (not in 802.3) */
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#define KS8721_MCR_DISABXMT (1 << 0) /* Bit 0: Disable Transmitter */
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/* KS8921 MII ID1/2 register bits */
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#define MII_PHYID1_KS8721 0x0022 /* ID1 value for Micrel KS8721 */
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#define MII_PHYID2_KS8721 0x1619 /* ID2 value for Micrel KS8721 */
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/* KS8921 RXER Counter -- 16-bit counter */
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/* KS8921 Interrupt Control/Status Register */
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#define KS8721_INTCS_LINKUP (1 << 0) /* Bit 0: Link up occurred */
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#define KS8721_INTCS_REMFAULT (1 << 1) /* Bit 1: Remote fault occurred */
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#define KS8721_INTCS_LINKDOWN (1 << 2) /* Bit 2: Link down occurred */
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#define KS8721_INTCS_LPACK (1 << 3) /* Bit 3: Link partner acknowlege occurred */
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#define KS8721_INTCS_PDFAULT (1 << 4) /* Bit 4: Parallel detect fault occurred */
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#define KS8721_INTCS_PGRCVD (1 << 5) /* Bit 5: Page received occurred */
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#define KS8721_INTCS_RXERR (1 << 6) /* Bit 6: Receive error occurred */
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#define KS8721_INTCS_JABBER (1 << 7) /* Bit 7: Jabber interrupt occurred */
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#define KS8721_INTCS_LINKUPE (1 << 8) /* Bit 8: Enable link up interrupt */
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#define KS8721_INTCS_REMFAULTE (1 << 9) /* Bit 9: Enable remote fault interrupt */
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#define KS8721_INTCS_LINKDOWNE (1 << 10) /* Bit 10: Enable link down interrupt */
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#define KS8721_INTCS_LPACKE (1 << 11) /* Bit 11: Enable link partner acknowldgement interrupt */
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#define KS8721_INTCS_PDFAULTE (1 << 12) /* Bit 12: Enable parallel detect fault interrupt */
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#define KS8721_INTCS_PGRCVDE (1 << 13) /* Bit 13: Enable page received interrupt */
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#define KS8721_INTCS_RXERRE (1 << 14) /* Bit 14: Enable receive error interrupt */
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#define KS8721_INTCS_JABBERE (1 << 15) /* Bit 15: Enable Jabber Interrupt */
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/* KS8921 10BASE-TX PHY control register */
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#define KS8721_10BTCR_BIT0 (1 << 0) /* Bit 0: xxx */
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#define KS8721_10BTCR_BIT1 (1 << 1) /* Bit 1: xxx */
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#define KS8721_10BTCR_MODE_SHIFT (2) /* Bits 2-4: Operation Mode Indication */
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#define KS8721_10BTCR_MODE_MASK (7 << KS8721_10BTCR_MODE_SHIFT)
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# define KS8721_10BTCR_MODE_ANEG (0 << KS8721_10BTCR_MODE_SHIFT) /* Still in auto-negotiation */
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# define KS8721_10BTCR_MODE_10BTHD (1 << KS8721_10BTCR_MODE_SHIFT) /* 10BASE-T half-duplex */
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# define KS8721_10BTCR_MODE_100BTHD (2 << KS8721_10BTCR_MODE_SHIFT) /* 100BASE_t half-duplex */
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# define KS8721_10BTCR_MODE_DEFAULT (3 << KS8721_10BTCR_MODE_SHIFT) /* Default */
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# define KS8721_10BTCR_MODE_10BTFD (5 << KS8721_10BTCR_MODE_SHIFT) /* 10BASE-T full duplex */
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# define KS8721_10BTCR_MODE_100BTFD (6 << KS8721_10BTCR_MODE_SHIFT) /* 100BASE-T full duplex */
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# define KS8721_10BTCR_MODE_ISOLATE (7 << KS8721_10BTCR_MODE_SHIFT) /* PHY/MII isolate */
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#define KS8721_10BTCR_ISOLATE (1 << 5) /* Bit 5: PHY isolate */
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#define KS8721_10BTCR_PAUSE (1 << 6) /* Bit 6: Enable pause */
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#define KS8721_10BTCR_ANEGCOMP (1 << 7) /* Bit 7: Auto-negotiation complete */
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#define KS8721_10BTCR_JABBERE (1 << 8) /* Bit 8: Enable Jabber */
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#define KS8721_10BTCR_INTLVL (1 << 9) /* Bit 9: Interrupt level */
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#define KS8721_10BTCR_POWER (1 << 10) /* Bit 10: Power saving */
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#define KS8721_10BTCR_FORCE (1 << 11) /* Bit 11: Force link */
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#define KS8721_10BTCR_ENERGY (1 << 12) /* Bit 12: Energy detect */
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#define KS8721_10BTCR_PAIRSWAPD (1 << 13) /* Bit 13: Pairswap disable */
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/****************************************************************************
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* Type Definitions
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C" {
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCLUDE_NUTTX_NET_MII_H */
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