355 lines
15 KiB
C
355 lines
15 KiB
C
/****************************************************************************
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* include/nuttx/serial/uart_16550.h
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* Serial driver for 16550 UART
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __INCLUDE_NUTTX_SERIAL_UART_16550_H
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#define __INCLUDE_NUTTX_SERIAL_UART_16550_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifdef CONFIG_16550_UART
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* CONFIGURATION ************************************************************/
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/* Are any UARTs enabled? */
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#undef HAVE_UART
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#if defined(CONFIG_16550_UART0) || defined(CONFIG_16550_UART1) || \
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defined(CONFIG_16550_UART2) || defined(CONFIG_16550_UART3)
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# define HAVE_UART 1
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#endif
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/* We need to be told the address increment between registers and the
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* register bit width.
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*/
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#ifndef CONFIG_16550_REGINCR
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# error "CONFIG_16550_REGINCR not defined"
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#endif
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#if CONFIG_16550_REGINCR != 1 && CONFIG_16550_REGINCR != 2 && CONFIG_16550_REGINCR != 4
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# error "CONFIG_16550_REGINCR not supported"
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#endif
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#ifndef CONFIG_16550_REGWIDTH
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# error "CONFIG_16550_REGWIDTH not defined"
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#endif
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#if CONFIG_16550_REGWIDTH != 8 && CONFIG_16550_REGWIDTH != 16 && CONFIG_16550_REGWIDTH != 32
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# error "CONFIG_16550_REGWIDTH not supported"
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#endif
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#ifndef CONFIG_16550_ADDRWIDTH
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# error "CONFIG_16550_ADDRWIDTH not defined"
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#endif
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#if CONFIG_16550_ADDRWIDTH != 0 && CONFIG_16550_ADDRWIDTH != 8 && \
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CONFIG_16550_ADDRWIDTH != 16 && CONFIG_16550_ADDRWIDTH != 32 && \
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CONFIG_16550_ADDRWIDTH != 64
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# error "CONFIG_16550_ADDRWIDTH not supported"
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#endif
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/* If a UART is enabled, then its base address, clock, and IRQ
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* must also be provided
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*/
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#ifdef CONFIG_16550_UART0
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# ifndef CONFIG_16550_UART0_BASE
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# error "CONFIG_16550_UART0_BASE not provided"
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# undef CONFIG_16550_UART0
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# endif
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# ifndef CONFIG_16550_UART0_CLOCK
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# error "CONFIG_16550_UART0_CLOCK not provided"
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# undef CONFIG_16550_UART0
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# endif
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# ifndef CONFIG_16550_UART0_IRQ
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# error "CONFIG_16550_UART0_IRQ not provided"
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# undef CONFIG_16550_UART0
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# endif
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#endif
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#ifdef CONFIG_16550_UART1
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# ifndef CONFIG_16550_UART1_BASE
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# error "CONFIG_16550_UART1_BASE not provided"
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# undef CONFIG_16550_UART1
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# endif
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# ifndef CONFIG_16550_UART1_CLOCK
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# error "CONFIG_16550_UART1_CLOCK not provided"
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# undef CONFIG_16550_UART1
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# endif
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# ifndef CONFIG_16550_UART1_IRQ
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# error "CONFIG_16550_UART1_IRQ not provided"
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# undef CONFIG_16550_UART1
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# endif
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#endif
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#ifdef CONFIG_16550_UART2
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# ifndef CONFIG_16550_UART2_BASE
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# error "CONFIG_16550_UART2_BASE not provided"
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# undef CONFIG_16550_UART2
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# endif
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# ifndef CONFIG_16550_UART2_CLOCK
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# error "CONFIG_16550_UART2_CLOCK not provided"
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# undef CONFIG_16550_UART2
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# endif
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# ifndef CONFIG_16550_UART2_IRQ
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# error "CONFIG_16550_UART2_IRQ not provided"
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# undef CONFIG_16550_UART2
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# endif
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#endif
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#ifdef CONFIG_16550_UART3
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# ifndef CONFIG_16550_UART3_BASE
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# error "CONFIG_16550_UART3_BASE not provided"
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# undef CONFIG_16550_UART3
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# endif
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# ifndef CONFIG_16550_UART3_CLOCK
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# error "CONFIG_16550_UART3_CLOCK not provided"
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# undef CONFIG_16550_UART3
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# endif
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# ifndef CONFIG_16550_UART3_IRQ
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# error "CONFIG_16550_UART3_IRQ not provided"
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# undef CONFIG_16550_UART3
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# endif
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#endif
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/* Is there a serial console? There should be at most one defined.
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* It could be on any UARTn, n=0,1,2,3
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*/
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#if defined(CONFIG_16550_UART0_SERIAL_CONSOLE) && defined(CONFIG_16550_UART0)
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# undef CONFIG_16550_UART1_SERIAL_CONSOLE
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# undef CONFIG_16550_UART2_SERIAL_CONSOLE
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# undef CONFIG_16550_UART3_SERIAL_CONSOLE
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# define HAVE_16550_CONSOLE 1
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#elif defined(CONFIG_16550_UART1_SERIAL_CONSOLE) && defined(CONFIG_16550_UART1)
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# undef CONFIG_16550_UART0_SERIAL_CONSOLE
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# undef CONFIG_16550_UART2_SERIAL_CONSOLE
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# undef CONFIG_16550_UART3_SERIAL_CONSOLE
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# define HAVE_16550_CONSOLE 1
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#elif defined(CONFIG_16550_UART2_SERIAL_CONSOLE) && defined(CONFIG_16550_UART2)
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# undef CONFIG_16550_UART0_SERIAL_CONSOLE
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# undef CONFIG_16550_UART1_SERIAL_CONSOLE
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# undef CONFIG_16550_UART3_SERIAL_CONSOLE
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# define HAVE_16550_CONSOLE 1
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#elif defined(CONFIG_16550_UART3_SERIAL_CONSOLE) && defined(CONFIG_16550_UART3)
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# undef CONFIG_16550_UART0_SERIAL_CONSOLE
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# undef CONFIG_16550_UART1_SERIAL_CONSOLE
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# undef CONFIG_16550_UART2_SERIAL_CONSOLE
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# define HAVE_16550_CONSOLE 1
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#else
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# undef CONFIG_16550_UART0_SERIAL_CONSOLE
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# undef CONFIG_16550_UART1_SERIAL_CONSOLE
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# undef CONFIG_16550_UART2_SERIAL_CONSOLE
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# undef CONFIG_16550_UART3_SERIAL_CONSOLE
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# undef HAVE_16550_CONSOLE
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#endif
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/* Register offsets *********************************************************/
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#define UART_RBR_INCR 0 /* (DLAB =0) Receiver Buffer Register */
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#define UART_THR_INCR 0 /* (DLAB =0) Transmit Holding Register */
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#define UART_DLL_INCR 0 /* (DLAB =1) Divisor Latch LSB */
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#define UART_DLM_INCR 1 /* (DLAB =1) Divisor Latch MSB */
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#define UART_IER_INCR 1 /* (DLAB =0) Interrupt Enable Register */
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#define UART_IIR_INCR 2 /* Interrupt ID Register */
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#define UART_FCR_INCR 2 /* FIFO Control Register */
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#define UART_LCR_INCR 3 /* Line Control Register */
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#define UART_MCR_INCR 4 /* Modem Control Register */
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#define UART_LSR_INCR 5 /* Line Status Register */
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#define UART_MSR_INCR 6 /* Modem Status Register */
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#define UART_SCR_INCR 7 /* Scratch Pad Register */
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#define UART_RBR_OFFSET (CONFIG_16550_REGINCR*UART_RBR_INCR)
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#define UART_THR_OFFSET (CONFIG_16550_REGINCR*UART_THR_INCR)
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#define UART_DLL_OFFSET (CONFIG_16550_REGINCR*UART_DLL_INCR)
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#define UART_DLM_OFFSET (CONFIG_16550_REGINCR*UART_DLM_INCR)
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#define UART_IER_OFFSET (CONFIG_16550_REGINCR*UART_IER_INCR)
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#define UART_IIR_OFFSET (CONFIG_16550_REGINCR*UART_IIR_INCR)
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#define UART_FCR_OFFSET (CONFIG_16550_REGINCR*UART_FCR_INCR)
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#define UART_LCR_OFFSET (CONFIG_16550_REGINCR*UART_LCR_INCR)
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#define UART_MCR_OFFSET (CONFIG_16550_REGINCR*UART_MCR_INCR)
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#define UART_LSR_OFFSET (CONFIG_16550_REGINCR*UART_LSR_INCR)
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#define UART_MSR_OFFSET (CONFIG_16550_REGINCR*UART_MSR_INCR)
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#define UART_SCR_OFFSET (CONFIG_16550_REGINCR*UART_SCR_INCR)
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/* Register bit definitions *************************************************/
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/* RBR (DLAB =0) Receiver Buffer Register */
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#define UART_RBR_MASK (0xff) /* Bits 0-7: Oldest received byte in RX FIFO */
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/* Bits 8-31: Reserved */
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/* THR (DLAB =0) Transmit Holding Register */
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#define UART_THR_MASK (0xff) /* Bits 0-7: Adds byte to TX FIFO */
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/* Bits 8-31: Reserved */
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/* DLL (DLAB =1) Divisor Latch LSB */
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#define UART_DLL_MASK (0xff) /* Bits 0-7: DLL */
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/* Bits 8-31: Reserved */
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/* DLM (DLAB =1) Divisor Latch MSB */
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#define UART_DLM_MASK (0xff) /* Bits 0-7: DLM */
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/* Bits 8-31: Reserved */
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/* IER (DLAB =0) Interrupt Enable Register */
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#define UART_IER_ERBFI (1 << 0) /* Bit 0: Enable received data available interrupt */
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#define UART_IER_ETBEI (1 << 1) /* Bit 1: Enable THR empty interrupt */
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#define UART_IER_ELSI (1 << 2) /* Bit 2: Enable receiver line status interrupt */
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#define UART_IER_EDSSI (1 << 3) /* Bit 3: Enable MODEM status interrupt */
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/* Bits 4-7: Reserved */
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#define UART_IER_ALLIE (0x0f)
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/* IIR Interrupt ID Register */
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#define UART_IIR_INTSTATUS (1 << 0) /* Bit 0: Interrupt status (active low) */
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#define UART_IIR_INTID_SHIFT (1) /* Bits 1-3: Interrupt identification */
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#define UART_IIR_INTID_MASK (7 << UART_IIR_INTID_SHIFT)
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# define UART_IIR_INTID_MSI (0 << UART_IIR_INTID_SHIFT) /* Modem Status */
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# define UART_IIR_INTID_THRE (1 << UART_IIR_INTID_SHIFT) /* THR Empty Interrupt */
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# define UART_IIR_INTID_RDA (2 << UART_IIR_INTID_SHIFT) /* Receive Data Available (RDA) */
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# define UART_IIR_INTID_RLS (3 << UART_IIR_INTID_SHIFT) /* Receiver Line Status (RLS) */
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# define UART_IIR_INTID_CTI (6 << UART_IIR_INTID_SHIFT) /* Character Time-out Indicator (CTI) */
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/* Bits 4-5: Reserved */
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#define UART_IIR_FIFOEN_SHIFT (6) /* Bits 6-7: RCVR FIFO interrupt */
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#define UART_IIR_FIFOEN_MASK (3 << UART_IIR_FIFOEN_SHIFT)
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/* FCR FIFO Control Register */
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#define UART_FCR_FIFOEN (1 << 0) /* Bit 0: Enable FIFOs */
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#define UART_FCR_RXRST (1 << 1) /* Bit 1: RX FIFO Reset */
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#define UART_FCR_TXRST (1 << 2) /* Bit 2: TX FIFO Reset */
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#define UART_FCR_DMAMODE (1 << 3) /* Bit 3: DMA Mode Select */
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/* Bits 4-5: Reserved */
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#define UART_FCR_RXTRIGGER_SHIFT (6) /* Bits 6-7: RX Trigger Level */
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#define UART_FCR_RXTRIGGER_MASK (3 << UART_FCR_RXTRIGGER_SHIFT)
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# define UART_FCR_RXTRIGGER_1 (0 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 0 (1 character) */
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# define UART_FCR_RXTRIGGER_4 (1 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 1 (4 characters) */
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# define UART_FCR_RXTRIGGER_8 (2 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 2 (8 characters) */
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# define UART_FCR_RXTRIGGER_14 (3 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 3 (14 characters) */
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/* LCR Line Control Register */
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#define UART_LCR_WLS_SHIFT (0) /* Bit 0-1: Word Length Select */
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#define UART_LCR_WLS_MASK (3 << UART_LCR_WLS_SHIFT)
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# define UART_LCR_WLS_5BIT (0 << UART_LCR_WLS_SHIFT)
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# define UART_LCR_WLS_6BIT (1 << UART_LCR_WLS_SHIFT)
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# define UART_LCR_WLS_7BIT (2 << UART_LCR_WLS_SHIFT)
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# define UART_LCR_WLS_8BIT (3 << UART_LCR_WLS_SHIFT)
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#define UART_LCR_STB (1 << 2) /* Bit 2: Number of Stop Bits */
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#define UART_LCR_PEN (1 << 3) /* Bit 3: Parity Enable */
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#define UART_LCR_EPS (1 << 4) /* Bit 4: Even Parity Select */
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#define UART_LCR_STICKY (1 << 5) /* Bit 5: Stick Parity */
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#define UART_LCR_BRK (1 << 6) /* Bit 6: Break Control */
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#define UART_LCR_DLAB (1 << 7) /* Bit 7: Divisor Latch Access Bit (DLAB) */
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/* MCR Modem Control Register */
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#define UART_MCR_DTR (1 << 0) /* Bit 0: DTR Control Source for DTR output */
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#define UART_MCR_RTS (1 << 1) /* Bit 1: Control Source for RTS output */
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#define UART_MCR_OUT1 (1 << 2) /* Bit 2: Auxiliary user-defined output 1 */
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#define UART_MCR_OUT2 (1 << 3) /* Bit 3: Auxiliary user-defined output 2 */
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#define UART_MCR_LPBK (1 << 4) /* Bit 4: Loopback Mode Select */
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#define UART_MCR_AFCE (1 << 5) /* Bit 5: Auto Flow Control Enable */
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/* Bit 6-7: Reserved */
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/* LSR Line Status Register */
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#define UART_LSR_DR (1 << 0) /* Bit 0: Data Ready */
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#define UART_LSR_OE (1 << 1) /* Bit 1: Overrun Error */
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#define UART_LSR_PE (1 << 2) /* Bit 2: Parity Error */
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#define UART_LSR_FE (1 << 3) /* Bit 3: Framing Error */
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#define UART_LSR_BI (1 << 4) /* Bit 4: Break Interrupt */
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#define UART_LSR_THRE (1 << 5) /* Bit 5: Transmitter Holding Register Empty */
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#define UART_LSR_TEMT (1 << 6) /* Bit 6: Transmitter Empty */
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#define UART_LSR_RXFE (1 << 7) /* Bit 7: Error in RX FIFO (RXFE) */
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/* SCR Scratch Pad Register */
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#define UART_SCR_MASK (0xff) /* Bits 0-7: SCR data */
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#if CONFIG_16550_REGWIDTH == 8
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typedef uint8_t uart_datawidth_t;
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#elif CONFIG_16550_REGWIDTH == 16
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typedef uint16_t uart_datawidth_t;
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#elif CONFIG_16550_REGWIDTH == 32
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typedef uint32_t uart_datawidth_t;
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#endif
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#if CONFIG_16550_ADDRWIDTH == 0
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typedef uintptr_t uart_addrwidth_t;
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#elif CONFIG_16550_ADDRWIDTH == 8
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typedef uint8_t uart_addrwidth_t;
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#elif CONFIG_16550_ADDRWIDTH == 16
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typedef uint16_t uart_addrwidth_t;
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#elif CONFIG_16550_ADDRWIDTH == 32
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typedef uint32_t uart_addrwidth_t;
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#elif CONFIG_16550_ADDRWIDTH == 64
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typedef uint64_t uart_addrwidth_t;
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#endif
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Functions Definitions
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****************************************************************************/
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/****************************************************************************
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* Name: uart_getreg(), uart_putreg(), uart_ioctl()
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*
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* Description:
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* These functions must be provided by the processor-specific code in order
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* to correctly access 16550 registers
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* uart_ioctl() is optional to provide custom IOCTLs
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*
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****************************************************************************/
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#ifndef CONFIG_SERIAL_UART_ARCH_MMIO
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uart_datawidth_t uart_getreg(uart_addrwidth_t base, unsigned int offset);
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void uart_putreg(uart_addrwidth_t base,
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unsigned int offset,
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uart_datawidth_t value);
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#endif
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struct file; /* Forward reference */
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int uart_ioctl(struct file *filep, int cmd, unsigned long arg);
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#endif /* CONFIG_16550_UART */
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#endif /* __INCLUDE_NUTTX_SERIAL_UART_16550_H */
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