anjiahao 7732791cd6 mempool:Add mail_info support for multiple pools ... Signed-off-by: anjiahao <anjiahao@xiaomi.com>		2023-06-08 23:56:40 +08:00
..
esp32	arch/xtensa/esp32: Add support for RTC IRQs	2023-01-21 12:27:35 +08:00
esp32s2	arch/xtensa/esp32s2: Add support for RTC IRQs	2023-02-04 18:28:10 -03:00
esp32s3	esp32s3/wifi: add support for Wi-Fi (Station mode)	2023-03-10 10:59:14 +02:00
lx6	…
lx7	…
xtensa	Indent the define statement by two spaces	2023-05-21 09:52:08 -03:00
.gitignore	…
arch.h	mempool:Add mail_info support for multiple pools	2023-06-08 23:56:40 +08:00
elf.h	…
inttypes.h	…
irq.h	xtensa: Define COMMON_CTX_REGS for chips without FPU (e.g. ESP32-S2)	2022-10-27 23:28:47 +08:00
limits.h	arch: Define WCHAR_[MIN|MAX] in arch/include/limits.h	2022-06-03 22:25:49 +03:00
loadstore.h	…
setjmp.h	…
simcall.h	…
spinlock.h	…
stdarg.h	…
syscall.h	xtensa: Add missing input operand on sys_call6 inline ASM	2022-05-18 15:46:57 +02:00
types.h	…