203 lines
9.1 KiB
C
203 lines
9.1 KiB
C
/****************************************************************************
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* arch/arm/include/max326xx/chip.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_MAX326XX_CHIP_H
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#define __ARCH_ARM_INCLUDE_MAX326XX_CHIP_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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/* Get customizations for each supported MAX326xx family. Only sizes and
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* numbers of things are provided here. See arch/arm/src/max326xx/Kconfig
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* for other, boolean configuration settings.
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*
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* MAX326xx Families are determined by sharing a common User Guide for the
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* chip specification:
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*
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* MAX32620/32621 Family: MAX32620 Rev C, User Guide, AN6242, Rev 2, 2/17
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* MAX32630/32632 Family: MAX32630 Rev B, User Guide, AN6349, Rev 0, 10/16
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* MAX32660 Family: MAX32660 User Guide, AN6659, Rev0, 7/18
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*/
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/* MAX32620/32621 Family:
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*
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* Part Flash SRAM Trust Pin/Package
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* (Mb) (Kb) Protection
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* MAX32620ICQ+ 2 256 No 100 TQFP
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* MAX32620IWG+ 2 256 No 81 WLP
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* MAX32620IWG+T 2 256 No 81 WLP
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* MAX32620IWGL+ 1 256 No 81 WLP
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* MAX32620IWGL+T 1 256 No 81 WLP
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* MAX32621ICQ+ 2 256 Yes 100 TQFP
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* MAX32621IWG+ 2 256 Yes 81 WLP
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* MAX32621IWG+T 2 256 Yes 81 WLP
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*/
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#if defined(CONFIG_ARCH_CHIP_MAX32620) || defined(CONFIG_ARCH_CHIP_MAX32621)
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/* Peripherals */
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# define MAX326_NWDOG 0 /* No Watchdog Timers */
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# define MAX326_NWWDOG 2 /* Two Windowed Watchdog Timers */
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# define MAX326_NRWDOG 1 /* One Recovery Watchdog Timer */
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# define MAX326_NWAKEUP 1 /* One Wakeup Timer */
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# define MAX326_NRTC 1 /* One RTC */
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# define MAX326_NCRC 1 /* One CRC16/32 */
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# define MAX326_NAES 1 /* One AES 128,192, 256 */
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# define MAX326_NUSB20 1 /* One USB 2.0 device */
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# define MAX326_NTMR32 6 /* Six 32-bit Timers */
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# define MAX326_NTMR8 0 /* No 8-bit Timers */
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# define MAX326_NPTENGINE 16 /* Sixteen pulse train engines */
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# define MAX326_NSPIM 3 /* Three SPI master */
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# define MAX326_NSPIS 1 /* One SPI slave */
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# define MAX326_NSPIXIP 1 /* One SPI XIP */
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# define MAX326_NI2SS 0 /* No I2S slave */
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# define MAX326_NI2CM 3 /* Three I2C master */
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# define MAX326_NI2CS 1 /* One I2C slave */
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# define MAX326_NUART 4 /* Four UARTs */
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# define MAX326_N1WIREM 1 /* One 1-Wire master */
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# define MAX326_NADC10 1 /* One 10-bit ADC */
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/* MAX32630/32632 Family:
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*
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* Part Flash SRAM Trust Secure Pin/Package
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* (Mb) (Kb) Protection Bootloader
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* MAX32630IWQ+ 2 512 No No 100 WLP
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* MAX32630IWQ+T 2 512 No No 100 WLP
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* MAX32630ICQ+ 2 512 No No 100 TQFP-EP
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* MAX32631IWQ+ 2 512 Yes No 100 WLP
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* MAX32631IWQ+T 2 512 Yes No 100 WLP
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* MAX32631ICQ+ 2 512 Yes No 100 TQFP-EP
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* MAX32632IWQ+ 2 512 Yes Yes 100 WLP
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* MAX32632IWQ+T 2 512 Yes Yes 100 WLP
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*/
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#elif defined(CONFIG_ARCH_CHIP_MAX32630) || defined(CONFIG_ARCH_CHIP_MAX32632)
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/* Peripherals */
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# define MAX326_NWDOG 0 /* No Watchdog Timers */
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# define MAX326_NWWDOG 2 /* Two Windowed Watchdog Timers */
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# define MAX326_NRWDOG 0 /* No Recovery Watchdog Timer */
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# define MAX326_NWAKEUP 1 /* One Wakeup Timer */
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# define MAX326_NRTC 1 /* One RTC */
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# define MAX326_NCRC 1 /* One CRC16/32 */
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# define MAX326_NAES 1 /* One AES 128,192, 256 */
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# define MAX326_NUSB20 1 /* One USB 2.0 device */
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# define MAX326_NTMR32 6 /* Six 32-bit Timers */
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# define MAX326_NTMR8 0 /* No 8-bit Timers */
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# define MAX326_NPTENGINE 16 /* Sixteen pulse train engines */
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# define MAX326_NSPIM 3 /* Three SPI master */
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# define MAX326_NSPIS 1 /* One SPI slave */
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# define MAX326_NSPIXIP 1 /* One SPI XIP */
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# define MAX326_NI2SS 0 /* No I2S slave */
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# define MAX326_NI2CM 3 /* Three I2C master */
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# define MAX326_NI2CS 1 /* One I2C slave */
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# define MAX326_NUART 4 /* Four UARTs */
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# define MAX326_N1WIREM 1 /* One 1-Wire master */
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# define MAX326_NADC10 1 /* One 10-bit ADC */
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/* MAX32660 Family:
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*
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* Part Flash SRAM Secure Pin/Package
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* (Mb) (Kb) Bootloader
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* MAX32660GWE+ 256 96 No 16 WLP
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* MAX32660GWE+T 256 96 No 16 WLP
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* MAX32660GTP+ 256 96 No 20 TQFN-EP
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* MAX32660GTP+T 256 96 No 20 TQFN-EP
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* MAX32660GTG+ 256 96 No 24 TQFN-EP
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* MAX32660GTG+T 256 96 No 24 TQFN-EP
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* MAX32660GWEBL+* 256 96 Yes 16 WLP
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* MAX32660GWEBL+T* 256 96 Yes 16 WLP
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* MAX32660GTGBL+* 256 96 Yes 24 TQFN-EP
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* MAX32660GTGBL+T* 256 96 Yes 24 TQFN-EP
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* MAX32660GWELA+* 128 64 No 16 WLP
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* MAX32660GWELA+T* 128 64 No 16 WLP
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* MAX32660GTGLA+* 128 64 No 24 TQFN-EP
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* MAX32660GTGLA+T* 128 64 No 24 TQFN-EP
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* MAX32660GWELB+* 64 32 No 16 WLP
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* MAX32660GWELB+T* 64 32 No 16 WLP
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* MAX32660GTGLB+* 64 32 No 24 TQFN-EP
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* MAX32660GTGLB+T* 64 32 No 24 TQFN-EP
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*/
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#elif defined(CONFIG_ARCH_CHIP_MAX32660)
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/* Peripherals */
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# define MAX326_NWDOG 1 /* One Watchdog Timer */
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# define MAX326_NWWDOG 0 /* No Windowed Watchdog Timers */
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# define MAX326_NRWDOG 0 /* No Recovery Watchdog Timer */
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# define MAX326_NWAKEUP 0 /* No Wakeup Timer */
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# define MAX326_NRTC 1 /* One RTC */
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# define MAX326_NCRC 0 /* No CRC16/32 */
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# define MAX326_NAES 0 /* No AES 128,192, 256 */
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# define MAX326_NUSB20 0 /* No USB 2.0 device */
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# define MAX326_NTMR32 2 /* Two 32-bit Timers */
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# define MAX326_NTMR8 1 /* One 8-bit Timers */
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# define MAX326_NPTENGINE 0 /* No pulse train engines */
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# define MAX326_NSPIM 2 /* Three SPI master */
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# define MAX326_NSPIS 2 /* Two SPI slave */
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# define MAX326_NSPIXIP 0 /* No SPI XIP */
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# define MAX326_NI2SS 1 /* One I2S slave */
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# define MAX326_NI2CM 2 /* Two I2C master */
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# define MAX326_NI2CS 2 /* One I2C slave */
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# define MAX326_NUART 2 /* Two UARTs */
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# define MAX326_N1WIREM 0 /* No 1-Wire master */
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# define MAX326_NADC10 0 /* No 10-bit ADC */
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#else
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# error Unrecognized MAX326XX chip
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#endif
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/* NVIC priority levels *****************************************************/
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/* Each priority field holds a priority value, 0x00-0xe0. The lower the
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* value, the greater the priority of the corresponding interrupt. The
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* processor implements only bits[7:4] of each field, bits[6:0] read as zero
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* and ignore writes.
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*/
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#define NVIC_SYSH_PRIORITY_MIN 0xe0 /* All bits[7:5] set is minimum priority */
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define NVIC_SYSH_PRIORITY_STEP 0x20 /* Eight priority levels in steps 0x20 */
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Functions Prototypes
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****************************************************************************/
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#endif /* __ARCH_ARM_INCLUDE_MAX326XX_CHIP_H */
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