247 lines
6.4 KiB
C
247 lines
6.4 KiB
C
/****************************************************************************
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* arch/avr/include/avr32/irq.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* This file should never be included directly but, rather, only indirectly
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* through nuttx/irq.h
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*/
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#ifndef __ARCH_AVR_INCLUDE_AVR32_IRQ_H
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#define __ARCH_AVR_INCLUDE_AVR32_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/irq.h>
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#include <arch/avr32/avr32.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* General notes about the AVR32 ABI:
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*
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* Scratch/Volatile Registers: r8-r12
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* Preserved/Static Registers: r0-r7
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* Parameter Passing: r12-R8 (in that order)
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*/
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/* Register state save array indices.
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*
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* The following registers are saved by the AVR32 hardware (for the case of
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* interrupts only). Note the registers are order in the opposite order the
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* they appear in memory (i.e., in the order of increasing address) because
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* this makes it easier to following the ordering of pushing on a push-down
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* stack.
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*/
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#define REG_R8 16
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#define REG_R9 15
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#define REG_R10 14
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#define REG_R11 13
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#define REG_R12 12
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#define REG_R14 11
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#define REG_R15 10
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#define REG_SR 9
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#define REG_LR REG_R14
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#define REG_PC REG_R15
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/* Additional registers saved in order have the full CPU context */
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#define REG_R13 8
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#define REG_SP REG_R13
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#define REG_R0 7
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#define REG_R1 6
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#define REG_R2 5
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#define REG_R3 4
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#define REG_R4 3
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#define REG_R5 2
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#define REG_R6 1
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#define REG_R7 0
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/* Size of the register state save array (in 32-bit words) */
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#define INTCONTEXT_REGS 8 /* r8-r12, lr, pc, sr */
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#define XCPTCONTEXT_REGS 17 /* Plus r0-r7, sp */
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#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS)
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/* This struct defines the way the registers are stored. */
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#ifndef __ASSEMBLY__
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struct xcptcontext
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{
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/* The following function pointer is non-zero if there are pending signals
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* to be processed.
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*/
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void *sigdeliver; /* Actual type is sig_deliver_t */
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/* These are saved copies of PC and SR used during signal processing.
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*
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* REVISIT: Because there is only one copy of these save areas,
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* only a single signal handler can be active. This precludes
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* queuing of signal actions. As a result, signals received while
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* another signal handler is executing will be ignored!
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*/
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uint32_t saved_pc;
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uint32_t saved_sr;
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/* Register save area */
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uint32_t regs[XCPTCONTEXT_REGS];
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};
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#endif
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/****************************************************************************
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* Inline functions
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/* Name: up_irq_save, up_irq_restore, and friends.
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*
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* NOTE: This function should never be called from application code and,
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* as a general rule unless you really know what you are doing, this
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* function should not be called directly from operation system code either:
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* Typically, the wrapper functions, enter_critical_section() and
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* leave_critical section(), are probably what you really want.
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*/
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/* Read the AVR32 status register */
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static inline uint32_t avr32_sr(void)
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{
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uint32_t sr;
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__asm__ __volatile__ (
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"mfsr\t%0,%1\n\t"
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: "=r" (sr)
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: "i" (AVR32_SR)
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);
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return sr;
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}
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/* Read the interrupt vector base address */
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static inline uint32_t avr32_evba(void)
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{
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uint32_t evba;
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__asm__ __volatile__ (
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"mfsr\t%0,%1\n\t"
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: "=r" (evba)
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: "i" (AVR32_EVBA)
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);
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return evba;
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}
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/* Return the current value of the stack pointer */
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static inline uint32_t up_getsp(void)
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{
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uint32_t retval;
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__asm__ __volatile__
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(
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"mov\t%0,sp\n\t"
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: "=r" (retval)
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:
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);
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return retval;
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}
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/* Return the current interrupt enable state and disable all interrupts */
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static inline irqstate_t up_irq_save(void)
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{
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irqstate_t sr = (irqstate_t)avr32_sr();
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__asm__ __volatile__ (
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"ssrf\t%0\n\t"
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"nop\n\t"
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"nop"
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:
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: "i" (AVR32_SR_GM_SHIFT)
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);
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return sr;
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}
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/* Restore saved interrupt state */
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static inline void up_irq_restore(irqstate_t flags)
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{
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if ((flags & AVR32_SR_GM_MASK) == 0)
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{
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__asm__ __volatile__ (
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"csrf\t%0\n\t"
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"nop\n\t"
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"nop"
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:
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: "i" (AVR32_SR_GM_SHIFT)
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);
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}
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}
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/* Return the current interrupt enable state and enable all interrupts */
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static inline irqstate_t up_irq_enable(void)
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{
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irqstate_t sr = (irqstate_t)avr32_sr();
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__asm__ __volatile__ (
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"csrf\t%0\n\t"
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"nop\n\t"
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"nop"
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:
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: "i" (AVR32_SR_GM_SHIFT)
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);
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return sr;
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}
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#endif /* __ASSEMBLY__ */
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif
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#endif /* __ARCH_AVR_INCLUDE_AVR32_IRQ_H */
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