285 lines
14 KiB
C
285 lines
14 KiB
C
/****************************************************************************
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* include/nuttx/power/bq769x0.h
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* Lower half driver for 769x0 battery monitor
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __INCLUDE_NUTTX_POWER_BQ769X0_H
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#define __INCLUDE_NUTTX_POWER_BQ769X0_H
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Chip variant definitions */
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#define CHIP_BQ76920 0
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#define CHIP_BQ76930 1
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#define CHIP_BQ76940 2
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/* Auxiliary Definitions */
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#define BQ769X0_BASE_GAIN 365 /* uV/LSB */
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#define BQ769X0_MAX_CELLS 15 /* No more than 15 cells per chip*/
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#define BQ769X0_BAL_REG_COUNT 3 /* CELBAL1, CELBAL2, CELBAL3 */
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#define BQ769X0_BAL_BITS_PER_REG 5
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#define BQ76920_MIN_CELL_COUNT 3
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#define BQ76920_MAX_CELL_COUNT 5
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#define BQ76930_MIN_CELL_COUNT 6
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#define BQ76930_MAX_CELL_COUNT 10
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#define BQ76940_MIN_CELL_COUNT 9
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#define BQ76940_MAX_CELL_COUNT 15
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#define BQ76920_TEMP_COUNT 1
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#define BQ76930_TEMP_COUNT 2
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#define BQ76940_TEMP_COUNT 3
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#define BQ769X0_CC_CFG_DEFAULT_VAL 0x19 /* Per Datasheet */
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#define BQ769X0_CELLBAL_MASK 0x1f /* 5 LSBs in each register */
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#define BQ769X0_CC_TIME 250 /* milliseconds per CC sample */
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#define BQ769X0_CC_POLL_INTERVAL 50 /* milliseconds (arbitrary) */
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#define BQ769X0_CC_SCALE 8440 /* nanovolts / LSB */
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/* BQ769x0 Register Definitions *********************************************/
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/* System Control & Configuration Registers */
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#define BQ769X0_REG_SYS_STAT 0x00
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#define BQ769X0_REG_CELLBAL1 0x01
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#define BQ769X0_REG_CELLBAL2 0x02 /* Only on BQ76930 and BQ76940 */
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#define BQ769X0_REG_CELLBAL3 0x03 /* Only on BQ76940 */
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#define BQ769X0_REG_SYS_CTRL1 0x04
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#define BQ769X0_REG_SYS_CTRL2 0x05
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#define BQ769X0_REG_PROTECT1 0x06
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#define BQ769X0_REG_PROTECT2 0x07
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#define BQ769X0_REG_PROTECT3 0x08
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#define BQ769X0_REG_OV_TRIP 0x09
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#define BQ769X0_REG_UV_TRIP 0x0a
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#define BQ769X0_REG_CC_CFG 0x0b
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/* Cell Voltage Registers
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* BQ76920 can use VC1 - VC5
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* BQ76930 can use VC1 - VC10
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* BQ76940 can use VC1 - VC15
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*/
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#define BQ769X0_REG_VC1_HI 0x0c
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#define BQ769X0_REG_VC1_LO 0x0d
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#define BQ769X0_REG_VC2_HI 0x0e
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#define BQ769X0_REG_VC2_LO 0x0f
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#define BQ769X0_REG_VC3_HI 0x10
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#define BQ769X0_REG_VC3_LO 0x11
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#define BQ769X0_REG_VC4_HI 0x12
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#define BQ769X0_REG_VC4_LO 0x13
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#define BQ769X0_REG_VC5_HI 0x14
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#define BQ769X0_REG_VC5_LO 0x15
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#define BQ769X0_REG_VC6_HI 0x16
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#define BQ769X0_REG_VC6_LO 0x17
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#define BQ769X0_REG_VC7_HI 0x18
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#define BQ769X0_REG_VC7_LO 0x19
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#define BQ769X0_REG_VC8_HI 0x1a
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#define BQ769X0_REG_VC8_LO 0x1b
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#define BQ769X0_REG_VC9_HI 0x1c
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#define BQ769X0_REG_VC9_LO 0x1d
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#define BQ769X0_REG_VC10_HI 0x1e
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#define BQ769X0_REG_VC10_LO 0x1f
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#define BQ769X0_REG_VC11_HI 0x20
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#define BQ769X0_REG_VC11_LO 0x21
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#define BQ769X0_REG_VC12_HI 0x22
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#define BQ769X0_REG_VC12_LO 0x23
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#define BQ769X0_REG_VC13_HI 0x24
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#define BQ769X0_REG_VC13_LO 0x25
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#define BQ769X0_REG_VC14_HI 0x26
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#define BQ769X0_REG_VC14_LO 0x27
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#define BQ769X0_REG_VC15_HI 0x28
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#define BQ769X0_REG_VC15_LO 0x29
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/* System Voltage, Temperature, and Current Registers */
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#define BQ769X0_REG_BAT_HI 0x2a
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#define BQ769X0_REG_BAT_LO 0x2b
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#define BQ769X0_REG_TS1_HI 0x2c
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#define BQ769X0_REG_TS1_LO 0x2d
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#define BQ769X0_REG_TS2_HI 0x2e
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#define BQ769X0_REG_TS2_LO 0x2f
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#define BQ769X0_REG_TS3_HI 0x30
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#define BQ769X0_REG_TS3_LO 0x31
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#define BQ769X0_REG_CC_HI 0x32
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#define BQ769X0_REG_CC_LO 0x33
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/* ADC Calibration Registers */
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#define BQ769X0_REG_ADCGAIN1 0x50
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#define BQ769X0_REG_ADCOFFSET 0x51
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#define BQ769X0_REG_ADCGAIN2 0x59
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/* REG_SYS_STAT */
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#define BQ769X0_CC_READY (1 << 7) /* Updated Coulomb counter reading is available */
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/* Bit 6: Reserved */
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#define BQ769X0_DEVICE_XREADY (1 << 5) /* Internal chip fault detected */
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#define BQ769X0_OVRD_ALERT (1 << 4) /* External pull-up detected on ALERT pin */
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#define BQ769X0_UV (1 << 3) /* Undervoltage fault */
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#define BQ769X0_OV (1 << 2) /* Overvoltage fault */
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#define BQ769X0_SCD (1 << 1) /* Short circuit in discharge fault */
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#define BQ769X0_OCD (1 << 0) /* Over current in discharge fault */
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#define BQ769X0_FAULT_MASK (0x3f) /* Bottom 6 bits */
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/* REG_SYS_CTRL1 */
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#define BQ769X0_LOAD_PRESENT (1 << 7) /* CHG pin is higher than VLOAD_DETECT, external load is present */
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/* Bit 6: Reserved */
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/* Bit 5: Reserved */
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#define BQ769X0_ADC_EN (1 << 4) /* Enable voltage, temperature measurement and OV protection */
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#define BQ769X0_TEMP_SEL (1 << 3) /* 0 = use onboard temp sensors, 1 = use external temp sensors */
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/* Bit 2: Reserved */
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#define BQ769X0_SHUT_A (1 << 1) /* Shutdown command, bit A */
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#define BQ769X0_SHUT_B (1 << 0) /* Shutdown command, bit B */
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#define BQ769X0_SYS_CTRL1_WRITE_MASK (0x1b) /* Bits 0, 1, 3, and 4 are writeable */
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#define BQ769X0_SYS_CTRL1_SHUTDOWN_MASK (0x03) /* Bits 0 and 1 for shutdown */
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/* REG_SYS_CTRL2 */
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#define BQ769X0_DELAY_DIS (1 << 7) /* 1 = Disable protection delays for testing */
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#define BQ769X0_CC_EN (1 << 6) /* 1 = Enable continuous Coulomb counter readings */
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#define BQ769X0_CC_ONESHOT (1 << 5) /* Trigger a single 250ms Coulomb counter read */
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/* Bit 4: Reserved */
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/* Bit 3: Reserved */
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/* Bit 2: Reserved */
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#define BQ769X0_DSG_ON (1 << 1) /* DSG (Discharge FET) control */
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#define BQ769X0_CHG_ON (1 << 0) /* CHG (Charge FET) control */
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#define BQ769X0_SYS_CTRL2_WRITE_MASK (0xe3) /* Bits 0, 1, 5, 6, and 7 are writeable */
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#define BQ769X0_SYS_CTRL2_CHGDSG_MASK (0x03) /* Bits 0 and 1 for charge/discharge */
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/* REG_PROTECT1 */
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#define BQ769X0_RSNS (1 << 7) /* Selects low or high input range for OCD/SCD */
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/* Bit 6: Reserved */
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/* Bit 5: Reserved */
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#define BQ769X0_SCD_DELAY_SHIFT (3) /* Short circuit in discharge delay timer */
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#define BQ769X0_SCD_DELAY_MASK (0x03 << BQ769X0_SCD_DELAY_SHIFT)
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# define BQ769X0_SCD_DELAY_70US (0 << BQ769X0_SCD_DELAY_SHIFT)
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# define BQ769X0_SCD_DELAY_100US (1 << BQ769X0_SCD_DELAY_SHIFT)
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# define BQ769X0_SCD_DELAY_200US (2 << BQ769X0_SCD_DELAY_SHIFT)
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# define BQ769X0_SCD_DELAY_400US (3 << BQ769X0_SCD_DELAY_SHIFT)
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#define BQ769X0_SCD_THRESH_SHIFT (0) /* Short circuit in discharge threshold value */
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#define BQ769X0_SCD_THRESH_MASK (0x07 << BQ769X0_SCD_THRESH_SHIFT)
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/* These defines apply when RSNS is 0 */
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# define BQ769X0_SCD_THRESH_0_22MV (0 << BQ769X0_SCD_THRESH_SHIFT)
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# define BQ769X0_SCD_THRESH_0_33MV (1 << BQ769X0_SCD_THRESH_SHIFT)
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# define BQ769X0_SCD_THRESH_0_44MV (2 << BQ769X0_SCD_THRESH_SHIFT)
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# define BQ769X0_SCD_THRESH_0_56MV (3 << BQ769X0_SCD_THRESH_SHIFT)
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# define BQ769X0_SCD_THRESH_0_67MV (4 << BQ769X0_SCD_THRESH_SHIFT)
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# define BQ769X0_SCD_THRESH_0_78MV (5 << BQ769X0_SCD_THRESH_SHIFT)
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# define BQ769X0_SCD_THRESH_0_89MV (6 << BQ769X0_SCD_THRESH_SHIFT)
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# define BQ769X0_SCD_THRESH_0_100MV (7 << BQ769X0_SCD_THRESH_SHIFT)
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/* These defines apply when RSNS is 1 */
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# define BQ769X0_SCD_THRESH_1_44MV (0 << BQ769X0_SCD_THRESH_SHIFT)
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# define BQ769X0_SCD_THRESH_1_67MV (1 << BQ769X0_SCD_THRESH_SHIFT)
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# define BQ769X0_SCD_THRESH_1_89MV (2 << BQ769X0_SCD_THRESH_SHIFT)
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# define BQ769X0_SCD_THRESH_1_111MV (3 << BQ769X0_SCD_THRESH_SHIFT)
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# define BQ769X0_SCD_THRESH_1_133MV (4 << BQ769X0_SCD_THRESH_SHIFT)
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# define BQ769X0_SCD_THRESH_1_155MV (5 << BQ769X0_SCD_THRESH_SHIFT)
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# define BQ769X0_SCD_THRESH_1_178MV (6 << BQ769X0_SCD_THRESH_SHIFT)
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# define BQ769X0_SCD_THRESH_1_200MV (7 << BQ769X0_SCD_THRESH_SHIFT)
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/* REG_PROTECT2 */
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/* Bit 7: Reserved */
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#define BQ769X0_OCD_DELAY_SHIFT (4) /* Over current in discharge delay timer */
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#define BQ769X0_OCD_DELAY_MASK (0x07 << BQ769X0_OCD_DELAY_SHIFT)
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# define BQ769X0_OCD_DELAY_8MS (0 << BQ769X0_OCD_DELAY_SHIFT)
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# define BQ769X0_OCD_DELAY_20MS (1 << BQ769X0_OCD_DELAY_SHIFT)
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# define BQ769X0_OCD_DELAY_40MS (2 << BQ769X0_OCD_DELAY_SHIFT)
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# define BQ769X0_OCD_DELAY_80MS (3 << BQ769X0_OCD_DELAY_SHIFT)
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# define BQ769X0_OCD_DELAY_160MS (4 << BQ769X0_OCD_DELAY_SHIFT)
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# define BQ769X0_OCD_DELAY_320MS (5 << BQ769X0_OCD_DELAY_SHIFT)
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# define BQ769X0_OCD_DELAY_640MS (6 << BQ769X0_OCD_DELAY_SHIFT)
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# define BQ769X0_OCD_DELAY_1280MS (7 << BQ769X0_OCD_DELAY_SHIFT)
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#define BQ769X0_OCD_THRESH_SHIFT (0) /* Over current in discharge threshold value */
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#define BQ769X0_OCD_THRESH_MASK (0x0f << BQ769X0_OCD_THRESH_SHIFT)
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/* These defines apply when RSNS is 0 */
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# define BQ769X0_OCD_THRESH_0_8MV (0 << BQ769X0_OCD_THRESH_SHIFT)
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# define BQ769X0_OCD_THRESH_0_11MV (1 << BQ769X0_OCD_THRESH_SHIFT)
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# define BQ769X0_OCD_THRESH_0_14MV (2 << BQ769X0_OCD_THRESH_SHIFT)
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# define BQ769X0_OCD_THRESH_0_17MV (3 << BQ769X0_OCD_THRESH_SHIFT)
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# define BQ769X0_OCD_THRESH_0_19MV (4 << BQ769X0_OCD_THRESH_SHIFT)
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# define BQ769X0_OCD_THRESH_0_22MV (5 << BQ769X0_OCD_THRESH_SHIFT)
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# define BQ769X0_OCD_THRESH_0_25MV (6 << BQ769X0_OCD_THRESH_SHIFT)
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# define BQ769X0_OCD_THRESH_0_28MV (7 << BQ769X0_OCD_THRESH_SHIFT)
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# define BQ769X0_OCD_THRESH_0_31MV (8 << BQ769X0_OCD_THRESH_SHIFT)
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# define BQ769X0_OCD_THRESH_0_33MV (9 << BQ769X0_OCD_THRESH_SHIFT)
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# define BQ769X0_OCD_THRESH_0_36MV (10 << BQ769X0_OCD_THRESH_SHIFT)
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# define BQ769X0_OCD_THRESH_0_39MV (11 << BQ769X0_OCD_THRESH_SHIFT)
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# define BQ769X0_OCD_THRESH_0_42MV (12 << BQ769X0_OCD_THRESH_SHIFT)
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# define BQ769X0_OCD_THRESH_0_44MV (13 << BQ769X0_OCD_THRESH_SHIFT)
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# define BQ769X0_OCD_THRESH_0_47MV (14 << BQ769X0_OCD_THRESH_SHIFT)
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# define BQ769X0_OCD_THRESH_0_50MV (15 << BQ769X0_OCD_THRESH_SHIFT)
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/* These defines apply when RSNS is 1 */
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# define BQ769X0_OCD_THRESH_1_17MV (0 << BQ769X0_OCD_THRESH_SHIFT)
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# define BQ769X0_OCD_THRESH_1_22MV (1 << BQ769X0_OCD_THRESH_SHIFT)
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# define BQ769X0_OCD_THRESH_1_28MV (2 << BQ769X0_OCD_THRESH_SHIFT)
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# define BQ769X0_OCD_THRESH_1_33MV (3 << BQ769X0_OCD_THRESH_SHIFT)
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# define BQ769X0_OCD_THRESH_1_39MV (4 << BQ769X0_OCD_THRESH_SHIFT)
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# define BQ769X0_OCD_THRESH_1_44MV (5 << BQ769X0_OCD_THRESH_SHIFT)
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# define BQ769X0_OCD_THRESH_1_50MV (6 << BQ769X0_OCD_THRESH_SHIFT)
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# define BQ769X0_OCD_THRESH_1_56MV (7 << BQ769X0_OCD_THRESH_SHIFT)
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# define BQ769X0_OCD_THRESH_1_61MV (8 << BQ769X0_OCD_THRESH_SHIFT)
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# define BQ769X0_OCD_THRESH_1_67MV (9 << BQ769X0_OCD_THRESH_SHIFT)
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# define BQ769X0_OCD_THRESH_1_72MV (10 << BQ769X0_OCD_THRESH_SHIFT)
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# define BQ769X0_OCD_THRESH_1_78MV (11 << BQ769X0_OCD_THRESH_SHIFT)
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# define BQ769X0_OCD_THRESH_1_83MV (12 << BQ769X0_OCD_THRESH_SHIFT)
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# define BQ769X0_OCD_THRESH_1_89MV (13 << BQ769X0_OCD_THRESH_SHIFT)
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# define BQ769X0_OCD_THRESH_1_94MV (14 << BQ769X0_OCD_THRESH_SHIFT)
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# define BQ769X0_OCD_THRESH_1_100MV (15 << BQ769X0_OCD_THRESH_SHIFT)
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/* REG_PROTECT3 */
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#define BQ769X0_UV_DELAY_SHIFT (6)
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#define BQ769X0_UV_DELAY_MASK (0x03 << BQ769X0_UV_DELAY_SHIFT)
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# define BQ769X0_UV_DELAY_1S (0 << BQ769X0_UV_DELAY_SHIFT)
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# define BQ769X0_UV_DELAY_4S (1 << BQ769X0_UV_DELAY_SHIFT)
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# define BQ769X0_UV_DELAY_8S (2 << BQ769X0_UV_DELAY_SHIFT)
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# define BQ769X0_UV_DELAY_16S (3 << BQ769X0_UV_DELAY_SHIFT)
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#define BQ769X0_OV_DELAY_SHIFT (4)
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#define BQ769X0_OV_DELAY_MASK (0x03 << BQ769X0_OV_DELAY_SHIFT)
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# define BQ769X0_OV_DELAY_1S (0 << BQ769X0_OV_DELAY_SHIFT)
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# define BQ769X0_OV_DELAY_2S (1 << BQ769X0_OV_DELAY_SHIFT)
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# define BQ769X0_OV_DELAY_4S (2 << BQ769X0_OV_DELAY_SHIFT)
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# define BQ769X0_OV_DELAY_8S (3 << BQ769X0_OV_DELAY_SHIFT)
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/* REG_ADCGAIN1 */
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#define BQ769X0_ADCGAIN1_SHIFT (2)
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#define BQ769X0_ADCGAIN1_MASK (0x03 << BQ769X0_ADCGAIN1_SHIFT)
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/* REG_ADCGAIN2 */
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#define BQ769X0_ADCGAIN2_SHIFT (5)
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#define BQ769X0_ADCGAIN2_MASK (0x07 << BQ769X0_ADCGAIN2_SHIFT)
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#endif /* __INCLUDE_NUTTX_POWER_BQ769X0_H */
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