266 lines
13 KiB
C
266 lines
13 KiB
C
/****************************************************************************
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* arch/arm/include/stm32h7/chip.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_STM32H7_CHIP_H
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#define __ARCH_ARM_INCLUDE_STM32H7_CHIP_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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/* STM32H7x3xx Differences between family members:
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*
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* ----------- ---------------- ----- ----
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* SPI
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* PART PACKAGE GPIOs I2S
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* ----------- ---------------- ----- ----
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* STM32H7x3Ax UFBGA169 132 6/3
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* STM32H7x3Bx LQFP208 168 6/3
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* STM32H7x3Ix LQFP176/UFBGA176 140 6/3
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* STM32H7x3Vx LQFP100/TFBGA100 82 5/3
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* STM32H7x3Xx TFBGA240 168 6/3
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* STM32H7x3Zx LQFP144 114 6/3
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* ----------- ---------------- ----- ----
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*
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* Parts STM32H7xxxG have 1024Kb of FLASH
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*
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* Parts STM32H7xxxI have 2048Kb of FLASH
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*
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* The correct FLASH size will be set CONFIG_STM32H7_FLASH_CONFIG_x or
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* overridden with CONFIG_STM32H7_FLASH_OVERRIDE_x
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*/
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#if defined (CONFIG_ARCH_CHIP_STM32H743AG) || \
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defined (CONFIG_ARCH_CHIP_STM32H743AI) || \
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defined (CONFIG_ARCH_CHIP_STM32H743BG) || \
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defined (CONFIG_ARCH_CHIP_STM32H743BI) || \
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defined (CONFIG_ARCH_CHIP_STM32H743IG) || \
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defined (CONFIG_ARCH_CHIP_STM32H743II) || \
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defined (CONFIG_ARCH_CHIP_STM32H743VG) || \
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defined (CONFIG_ARCH_CHIP_STM32H743VI) || \
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defined (CONFIG_ARCH_CHIP_STM32H743XG) || \
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defined (CONFIG_ARCH_CHIP_STM32H743XI) || \
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defined (CONFIG_ARCH_CHIP_STM32H743ZG) || \
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defined (CONFIG_ARCH_CHIP_STM32H743ZI) || \
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defined (CONFIG_ARCH_CHIP_STM32H753AI) || \
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defined (CONFIG_ARCH_CHIP_STM32H753BI) || \
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defined (CONFIG_ARCH_CHIP_STM32H753II) || \
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defined (CONFIG_ARCH_CHIP_STM32H753VI) || \
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defined (CONFIG_ARCH_CHIP_STM32H753XI) || \
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defined (CONFIG_ARCH_CHIP_STM32H753ZI) || \
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defined (CONFIG_ARCH_CHIP_STM32H7B3LI) || \
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defined (CONFIG_ARCH_CHIP_STM32H745XI) || \
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defined (CONFIG_ARCH_CHIP_STM32H745ZI) || \
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defined (CONFIG_ARCH_CHIP_STM32H755II)
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#elif defined(CONFIG_ARCH_CHIP_STM32H747XI)
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#else
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# error STM32 H7 chip not identified
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#endif
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/* Size SRAM */
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#if defined(CONFIG_STM32H7_STM32H7X3XX) || defined(CONFIG_STM32H7_STM32H7X5XX)
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/* Memory */
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# define STM32H7_SRAM_SIZE (512*1024) /* 512Kb SRAM on AXI bus Matrix (D1) */
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# define STM32H7_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix (D2) */
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# define STM32H7_SRAM2_SIZE (128*1024) /* 128Kb SRAM2 on AHB bus Matrix (D2) */
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# define STM32H7_SRAM3_SIZE (32*1024) /* 32Kb SRAM3 on AHB bus Matrix (D2) */
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# define STM32H7_SRAM123_SIZE (288*1024) /* 128Kb SRAM123 on AHB bus Matrix (D2) */
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# define STM32H7_SRAM4_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix (D3) */
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# if defined(CONFIG_ARMV7M_HAVE_DTCM)
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# define STM32H7_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */
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# else
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# define STM32H7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */
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# endif
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# if defined(CONFIG_ARMV7M_HAVE_ITCM)
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# define STM32H7_ITCM_SRAM_SIZE (64*1024) /* 64b ITCM SRAM on TCM interface */
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# else
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# define STM32H7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */
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# endif
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/* Peripherals */
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# if defined(CONFIG_STM32H7_IO_CONFIG_A)
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# define STM32H7_NGPIO (10) /* GPIOA-GPIOJ */
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# elif defined(CONFIG_STM32H7_IO_CONFIG_B)
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# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */
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# elif defined(CONFIG_STM32H7_IO_CONFIG_I)
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# define STM32H7_NGPIO (9) /* GPIOA-GPIOI */
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# elif defined(CONFIG_STM32H7_IO_CONFIG_V)
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# define STM32H7_NGPIO (8) /* GPIOA-GPIOH, missing GPIOF-GPIOG */
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# elif defined(CONFIG_STM32H7_IO_CONFIG_X)
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# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */
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# elif defined(CONFIG_STM32H7_IO_CONFIG_Z)
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# define STM32H7_NGPIO (8) /* GPIOA-GPIOH */
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# else
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# error CONFIG_STM32H7_IO_CONFIG_x Not Set
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# endif
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# define STM32H7_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */
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# define STM32H7_NADC (3) /* (3) ADC1-3*/
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# define STM32H7_NDAC (2) /* (2) DAC1-2*/
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# define STM32H7_NCMP (2) /* (2) ultra-low power comparators */
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# define STM32H7_NPGA (2) /* (2) Operational amplifiers: OPAMP */
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# define STM32H7_NDFSDM (1) /* (1) digital filters for sigma delta modulator */
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# define STM32H7_NUSART (4) /* (4) USART1-3, 6 */
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# define STM32H7_NSPI (6) /* (6) SPI1-6 */
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# define STM32H7_NI2S (3) /* (3) I2S1-3 */
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# define STM32H7_NUART (4) /* (4) UART4-5, 7-8 */
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# define STM32H7_NI2C (4) /* (4) I2C1-4 */
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# define STM32H7_NSAI (4) /* (4) SAI1-4*/
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# define STM32H7_NCAN (2) /* (2) CAN1-2 */
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# define STM32H7_NSDIO (2) /* (2) SDIO */
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#elif defined(CONFIG_STM32H7_STM32H7B3XX)
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/* Memory */
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# define STM32H7_SRAM_SIZE (1024*1024) /* 1024Kb SRAM on AXI bus Matrix (D1) */
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# define STM32H7_SRAM1_SIZE (64*1024) /* 64Kb SRAM1 on AHB bus Matrix (D2) */
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# define STM32H7_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix (D2) */
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# define STM32H7_SRAM3_SIZE (0*1024) /* No SRAM3 on AHB bus Matrix (D2) */
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# define STM32H7_SRAM123_SIZE (128*1024) /* 128Kb SRAM123 on AHB bus Matrix (D2) */
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# define STM32H7_SRAM4_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix (D3) */
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# if defined(CONFIG_ARMV7M_HAVE_DTCM)
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# define STM32H7_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */
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# else
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# define STM32H7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */
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# endif
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# if defined(CONFIG_ARMV7M_HAVE_ITCM)
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# define STM32H7_ITCM_SRAM_SIZE (64*1024) /* 64b ITCM SRAM on TCM interface */
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# else
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# define STM32H7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */
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# endif
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/* Peripherals */
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# if defined(CONFIG_STM32H7_IO_CONFIG_A)
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# define STM32H7_NGPIO (10) /* GPIOA-GPIOJ */
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# elif defined(CONFIG_STM32H7_IO_CONFIG_B)
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# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */
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# elif defined(CONFIG_STM32H7_IO_CONFIG_I)
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# define STM32H7_NGPIO (9) /* GPIOA-GPIOI */
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# elif defined(CONFIG_STM32H7_IO_CONFIG_L)
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# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */
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# elif defined(CONFIG_STM32H7_IO_CONFIG_V)
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# define STM32H7_NGPIO (8) /* GPIOA-GPIOH, missing GPIOF-GPIOG */
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# elif defined(CONFIG_STM32H7_IO_CONFIG_X)
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# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */
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# elif defined(CONFIG_STM32H7_IO_CONFIG_Z)
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# define STM32H7_NGPIO (8) /* GPIOA-GPIOH */
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# else
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# error CONFIG_STM32H7_IO_CONFIG_x Not Set
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# endif
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# define STM32H7_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */
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# define STM32H7_NADC (3) /* (3) ADC1-3*/
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# define STM32H7_NDAC (2) /* (2) DAC1-2*/
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# define STM32H7_NCMP (2) /* (2) ultra-low power comparators */
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# define STM32H7_NPGA (2) /* (2) Operational amplifiers: OPAMP */
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# define STM32H7_NDFSDM (1) /* (1) digital filters for sigma delta modulator */
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# define STM32H7_NUSART (4) /* (4) USART1-3, 6 */
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# define STM32H7_NSPI (6) /* (6) SPI1-6 */
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# define STM32H7_NI2S (3) /* (3) I2S1-3 */
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# define STM32H7_NUART (4) /* (4) UART4-5, 7-8 */
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# define STM32H7_NI2C (4) /* (4) I2C1-4 */
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# define STM32H7_NSAI (4) /* (4) SAI1-4*/
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# define STM32H7_NCAN (2) /* (2) CAN1-2 */
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# define STM32H7_NSDIO (2) /* (2) SDIO */
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#elif defined(CONFIG_STM32H7_STM32H7X7XX)
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/* Memory */
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# define STM32H7_SRAM_SIZE (512*1024) /* 512Kb SRAM on AXI bus Matrix (D1) */
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# define STM32H7_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix (D2) */
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# define STM32H7_SRAM2_SIZE (128*1024) /* 128Kb SRAM2 on AHB bus Matrix (D2) */
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# define STM32H7_SRAM3_SIZE (32*1024) /* 32Kb SRAM3 on AHB bus Matrix (D2) */
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# define STM32H7_SRAM123_SIZE (288*1024) /* 128Kb SRAM123 on AHB bus Matrix (D2) */
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# define STM32H7_SRAM4_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix (D3) */
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# if defined(CONFIG_ARMV7M_HAVE_DTCM)
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# define STM32H7_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */
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# else
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# define STM32H7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */
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# endif
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# if defined(CONFIG_ARMV7M_HAVE_ITCM)
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# define STM32H7_ITCM_SRAM_SIZE (64*1024) /* 64b ITCM SRAM on TCM interface */
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# else
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# define STM32H7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */
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# endif
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/* Peripherals */
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# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */
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# define STM32H7_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */
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# define STM32H7_NADC (3) /* (3) ADC1-3*/
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# define STM32H7_NDAC (2) /* (2) DAC1-2*/
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# define STM32H7_NCMP (2) /* (2) ultra-low power comparators */
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# define STM32H7_NPGA (2) /* (2) Operational amplifiers: OPAMP */
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# define STM32H7_NDFSDM (1) /* (1) digital filters for sigma delta modulator */
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# define STM32H7_NUSART (4) /* (4) USART1-3, 6 */
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# define STM32H7_NSPI (6) /* (6) SPI1-6 */
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# define STM32H7_NI2S (3) /* (3) I2S1-3 */
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# define STM32H7_NUART (4) /* (4) UART4-5, 7-8 */
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# define STM32H7_NI2C (4) /* (4) I2C1-4 */
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# define STM32H7_NSAI (4) /* (4) SAI1-4*/
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# define STM32H7_NCAN (2) /* (2) CAN1-2 */
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# define STM32H7_NSDIO (2) /* (2) SDIO */
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#else
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# error STM32 H7 chip Family not identified
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#endif
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/* TBD FPU Configuration */
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#if defined(CONFIG_ARCH_HAVE_FPU)
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#else
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#endif
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#if defined(CONFIG_ARCH_HAVE_DPFPU)
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#else
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#endif
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/* Diversification based on Family and package */
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#if defined(CONFIG_STM32H7_HAVE_ETHERNET)
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# define STM32H7_NETHERNET 1 /* 100/100 Ethernet MAC */
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#else
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# define STM32H7_NETHERNET 0 /* No 100/100 Ethernet MAC */
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#endif
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#if defined(CONFIG_STM32H7_HAVE_FMC)
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# define STM32H7_NFMC 1 /* Have FMC memory controller */
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#else
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# define STM32H7_NFMC 0 /* No FMC memory controller */
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#endif
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/* NVIC priority levels *****************************************************/
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/* 16 Programmable interrupt levels */
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#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */
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#endif /* __ARCH_ARM_INCLUDE_STM32H7_CHIP_H */
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