200 lines
11 KiB
C
200 lines
11 KiB
C
/****************************************************************************
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* arch/arm/include/kinetis/kinetis_dma.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_KINETIS_KINETIS_DMA_H
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#define __ARCH_ARM_INCLUDE_KINETIS_KINETIS_DMA_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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/* Note: It is envisioned that in the long term as a chip is added. The
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* author of the new chip definitions will either find the exact
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* configuration in an existing chip define and add the new chip to it Or add
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* the DMA feature configuration #defines to the chip ifdef list below. In
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* either case the author should mark it as "Verified to Document Number:"
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* taken from the reference manual.
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*/
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/* DMA Register Configuration
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*
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* KINETIS_DMA_HAS_CR_ERGA - DMA has CR[ERGA]
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* KINETIS_DMA_HAS_CR_GRP0PRI - DMA has CR[GRP0PRI]
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* KINETIS_DMA_HAS_CR_GRP1PRI - DMA has CR[GRP1PRI]
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* KINETIS_DMA_HAS_ES_ERRCHN - DMA has ES[ERRCHN]
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* KINETIS_DMA_HAS_ES_ERRCHN_BITS - DMA has 4 bit ES[ERRCHN]
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* KINETIS_DMA_HAS_ES_GPE - DMA has ES[GPE]
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* KINETIS_DMA_HAS_CEEI_CEEI_BITS - DMA has 4 bit CEEi[CEEI]
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* KINETIS_DMA_HAS_SEEI_SEEI_BITS - DMA has 4 bit SEEi[SEEI]
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* KINETIS_DMA_HAS_CERQ_CERQ_BITS - DMA has 4 bit CERQ[CERQ]
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* KINETIS_DMA_HAS_SERQ_SERQ_BITS - DMA has 4 bit SERQ[SERQ]
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* KINETIS_DMA_HAS_CDNE_CDNE_BITS - DMA has 4 bit CDNE[CDNE]
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* KINETIS_DMA_HAS_SSRT_SSRT_BITS - DMA has 4 bit SSRT[SSRT]
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* KINETIS_DMA_HAS_CERR_CERR_BITS - DMA has 4 bit CERR[CERR]
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* KINETIS_DMA_HAS_CINT_CINT_BITS - DMA has 4 bit CINT[CINT]
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* KINETIS_DMA_HAS_DCHPRI_CHPRI_BITS - DMA has 4 bit DCHPRI[DCHPRI]
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* KINETIS_DMA_HAS_DCHPRI_GRPPRI - DMA has DCHPRI[GRPPRI]
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* KINETIS_DMA_HAS_EARS - DMA has EARS Register
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* KINETIS_DMA_HAS_TCD_CITER1_LINKCH_BITS - DMA has 4 bit
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* TCD_CITER[LINKCH]
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* KINETIS_DMA_HAS_TCD_CSR_MAJORLINKCH_BITS - DMA has 4 bit
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* TCD_CSR[MAJORLINKCH]
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* KINETIS_DMA_HAS_TCD_BITER1_LINKCH_BITS - DMA has 4 bit
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* TCD_BITER[LINKCH]
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*/
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/* Describe the version of the DMA
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*
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* These defines are not related to any NXP reference but are merely
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* a way to label the versions we are using
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*/
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#define KINETIS_DMA_VERSION_UKN -1 /* What was in nuttx prior to 8/9/2018 */
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#define KINETIS_DMA_VERSION_01 1 /* Verified Document Number:
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* K60P144M100SF2V2RM Rev. 2, Jun 2012
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* K64P144M120SF5RM Rev. 2, Jan 2014
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*/
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#define KINETIS_DMA_VERSION_02 2 /* Verified Document Number:
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* K60P144M150SF3RM Rev. 3, Nov 2014
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* K66P144M180SF5RMV2 Rev. 2, May 2015
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*/
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#if defined(CONFIG_ARCH_CHIP_MK60DN256VLQ10) || defined(CONFIG_ARCH_CHIP_MK60DX256VLQ10) || \
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defined(CONFIG_ARCH_CHIP_MK60DN512VLQ10) || defined(CONFIG_ARCH_CHIP_MK60DN256VMD10) || \
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defined(CONFIG_ARCH_CHIP_MK60DX256VMD10) || defined(CONFIG_ARCH_CHIP_MK60DN512VMD10)
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/* Verified to Document Number: K60P144M100SF2V2RM Rev. 2 Jun 2012 */
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# define KINETIS_DMA_VERSION KINETIS_DMA_VERSION_01
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#elif defined(CONFIG_ARCH_CHIP_MK60FX512VLQ12) || defined(CONFIG_ARCH_CHIP_MK60FN1M0VLQ12) || \
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defined(CONFIG_ARCH_CHIP_MK60FX512VMD12) || defined(CONFIG_ARCH_CHIP_MK60FN1M0VMD12) || \
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defined(CONFIG_ARCH_CHIP_MK60FX512VLQ15) || defined(CONFIG_ARCH_CHIP_MK60FN1M0VLQ15) || \
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defined(CONFIG_ARCH_CHIP_MK60FX512VMD15) || defined(CONFIG_ARCH_CHIP_MK60FN1M0VMD15)
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/* Verified Document Number: K60P144M150SF3RM Rev. 3, Nov 2014 */
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# define KINETIS_DMA_VERSION KINETIS_DMA_VERSION_02
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#elif defined(CONFIG_ARCH_CHIP_MK64FN1M0VLL12) || defined(CONFIG_ARCH_CHIP_MK64FX512VLL12) || \
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defined(CONFIG_ARCH_CHIP_MK64FX512VDC12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VDC12) || \
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defined(CONFIG_ARCH_CHIP_MK64FX512VLQ12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VLQ12) || \
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defined(CONFIG_ARCH_CHIP_MK64FX512VMD12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VMD12)
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/* Verified to Document Number: K64P144M120SF5RM Rev. 2, January 2014 */
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# define KINETIS_DMA_VERSION KINETIS_DMA_VERSION_01
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/* MK66F N/X 1M0/2M0 V MD/LQ 18
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*
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* --------------- ------- --- ------- ------- ------ ------ ------ -----
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* PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO
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* FREQ CNT FLASH FLASH
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* --------------- ------- --- ------- ------- ------ ------ ------ -----
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* MK66FN2M0VMD18 180 MHz 144 MAPBGA 2 MB — — KB 260 KB 100
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* MK66FX1M0VMD18 180 MHz 144 MAPBGA 1.25 MB 1 MB 4 KB 256 KB 100
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* MK66FN2M0VLQ18 180 MHz 144 LQFP 2 MB — — KB 260 KB 100
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* MK66FX1M0VLQ18 180 MHz 144 LQFP 1.25 MB 1 MB 4 KB 256 KB 100
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*/
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#elif defined(CONFIG_ARCH_CHIP_MK66FN2M0VMD18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VMD18) || \
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defined(CONFIG_ARCH_CHIP_MK66FN2M0VLQ18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VLQ18)
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/* Verified to Document Number:
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* Document Number: K66P144M180SF5RMV2 Rev. 2, May 2015
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*/
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# define KINETIS_DMA_VERSION KINETIS_DMA_VERSION_02
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#else
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# define KINETIS_DMA_VERSION KINETIS_DMA_VERSION_UKN
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#endif
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/* Use the catch all configuration for the DMA based on
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* the implementations in nuttx prior 8/10/2018
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*/
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#if KINETIS_DMA_VERSION == KINETIS_DMA_VERSION_UKN
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/* DMA Register Configuration */
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#if defined(CONFIG_KINETIS_DMA)
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# warning "DMA Unsupported on this Kinetis device!"
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#endif
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#elif KINETIS_DMA_VERSION == KINETIS_DMA_VERSION_01
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/* DMA Register Configuration */
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# undef DMA_CHN_PER_GROUP /* Number of channels per group */
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# undef KINETIS_DMA_HAS_CR_ERGA /* DMA has CR[ERGA ] */
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# undef KINETIS_DMA_HAS_CR_GRP0PRI /* DMA has CR[GRP0PRI] */
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# undef KINETIS_DMA_HAS_CR_GRP1PRI /* DMA has CR[GRP1PRI] */
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# define KINETIS_DMA_HAS_ES_ERRCHN 1 /* DMA has ES[ERRCHN] */
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# define KINETIS_DMA_HAS_ES_ERRCHN_BITS 4 /* DMA has 4 bit ES[ERRCHN] */
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# undef KINETIS_DMA_HAS_ES_GPE /* DMA has ES[GPE ] */
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# define KINETIS_DMA_HAS_CEEI_CEEI_BITS 4 /* DMA has 4 bit CEEi[CEEI]*/
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# define KINETIS_DMA_HAS_SEEI_SEEI_BITS 4 /* DMA has 4 bit SEEi[SEEI]*/
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# define KINETIS_DMA_HAS_CERQ_CERQ_BITS 4 /* DMA has 4 bit CERQ[CERQ]*/
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# define KINETIS_DMA_HAS_SERQ_SERQ_BITS 4 /* DMA has 4 bit SERQ[SERQ]*/
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# define KINETIS_DMA_HAS_CDNE_CDNE_BITS 4 /* DMA has 4 bit CDNE[CDNE]*/
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# define KINETIS_DMA_HAS_SSRT_SSRT_BITS 4 /* DMA has 4 bit SSRT[SSRT]*/
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# define KINETIS_DMA_HAS_CERR_CERR_BITS 4 /* DMA has 4 bit CERR[CERR]*/
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# define KINETIS_DMA_HAS_CINT_CINT_BITS 4 /* DMA has 4 bit CINT[CINT]*/
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# define KINETIS_DMA_HAS_DCHPRI_CHPRI_BITS 4 /* DMA has 4 bit DCHPRI[DCHPRI]*/
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# undef KINETIS_DMA_HAS_DCHPRI_GRPPRI /* DMA has DCHPRI[GRPPRI] */
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# undef KINETIS_DMA_HAS_EARS /* DMA has EARS Register */
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# define KINETIS_DMA_HAS_TCD_CITER1_LINKCH_BITS 4 /* DMA has 4 bit TCD_CITER[LINKCH] */
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# define KINETIS_DMA_HAS_TCD_CSR_MAJORLINKCH_BITS 4 /* DMA has 4 bit TCD_CSR[MAJORLINKCH] */
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# define KINETIS_DMA_HAS_TCD_BITER1_LINKCH_BITS 4 /* DMA has 4 bit TCD_BITER[LINKCH] */
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#elif KINETIS_DMA_VERSION == KINETIS_DMA_VERSION_02
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/* DMA Register Configuration */
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# define DMA_CHN_PER_GROUP 16 /* Number of channels per group */
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# define KINETIS_DMA_HAS_CR_ERGA 1 /* DMA has CR[ERGA ] */
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# define KINETIS_DMA_HAS_CR_GRP0PRI 1 /* DMA has CR[GRP0PRI] */
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# define KINETIS_DMA_HAS_CR_GRP1PRI 1 /* DMA has CR[GRP1PRI] */
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# define KINETIS_DMA_HAS_ES_ERRCHN_BITS 5 /* DMA has 5 bit ES[ERRCHN] */
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# define KINETIS_DMA_HAS_ES_GPE 1 /* DMA has ES[GPE ] */
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# define KINETIS_DMA_HAS_CEEI_CEEI_BITS 5 /* DMA has 5 bit CEEI[CEEI]*/
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# define KINETIS_DMA_HAS_SEEI_SEEI_BITS 5 /* DMA has 5 bit SEEI[SEEI]*/
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# define KINETIS_DMA_HAS_CERQ_CERQ_BITS 5 /* DMA has 5 bit CERQ[CERQ]*/
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# define KINETIS_DMA_HAS_SERQ_SERQ_BITS 5 /* DMA has 5 bit SERQ[SERQ]*/
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# define KINETIS_DMA_HAS_CDNE_CDNE_BITS 5 /* DMA has 5 bit CDNE[CDNE]*/
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# define KINETIS_DMA_HAS_SSRT_SSRT_BITS 5 /* DMA has 5 bit SSRT[SSRT]*/
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# define KINETIS_DMA_HAS_CERR_CERR_BITS 5 /* DMA has 5 bit CERR[CERR]*/
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# define KINETIS_DMA_HAS_CINT_CINT_BITS 5 /* DMA has 5 bit CINT[CINT]*/
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# define KINETIS_DMA_HAS_DCHPRI_CHPRI_BITS 5 /* DMA has 5 bit DCHPRI[DCHPRI]*/
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# define KINETIS_DMA_HAS_DCHPRI_GRPPRI 1 /* DMA has DCHPRI[GRPPRI] */
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# define KINETIS_DMA_HAS_EARS 1 /* DMA has EARS Register */
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# define KINETIS_DMA_HAS_TCD_CITER1_LINKCH_BITS 5 /* DMA has 5 bit TCD_CITER[LINKCH] */
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# define KINETIS_DMA_HAS_TCD_CSR_MAJORLINKCH_BITS 5 /* DMA has 5 bit TCD_CSR[MAJORLINKCH] */
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# define KINETIS_DMA_HAS_TCD_BITER1_LINKCH_BITS 5 /* DMA has 5 bit TCD_BITER[LINKCH] */
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#endif
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#endif /* __ARCH_ARM_INCLUDE_KINETIS_KINETIS_DMA_H */
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