242 lines
11 KiB
C
242 lines
11 KiB
C
/****************************************************************************
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* arch/risc-v/include/esp32c3-legacy/irq.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_RISCV_INCLUDE_ESP32C3_IRQ_H
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#define __ARCH_RISCV_INCLUDE_ESP32C3_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define ESP32C3_INT_PRIO_DEF 1
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/* Interrupt Matrix
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*
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* The Interrupt Matrix embedded in the ESP32C3 independently allocates
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* peripheral interrupt sources to the CPUs’ peripheral interrupts.
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* This configuration is highly flexible in order to meet many different
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* needs.
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*
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* Features
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* - Accepts 62 peripheral interrupt sources as input.
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* - Generate 31 peripheral interrupts to CPU as output.
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* - Queries current interrupt status of peripheral interrupt sources.
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*/
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/* RESERVED interrupts: 0 to 14 */
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#define ESP32C3_PERIPH_WMAC 1 /* Reserved, but needed by WiFi driver */
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#define ESP32C3_PERIPH_BT_BB 5 /* Reserved, but needed by BLE driver */
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#define ESP32C3_PERIPH_RWBLE 8 /* Reserved, but needed by BLE driver */
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#define ESP32C3_PERIPH_UHCI0 15
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#define ESP32C3_PERIPH_GPIO 16
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#define ESP32C3_PERIPH_GPIO_NMI 17
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/* RESERVED interrupt 18 */
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#define ESP32C3_PERIPH_SPI2 19
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#define ESP32C3_PERIPH_I2S1 20
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#define ESP32C3_PERIPH_UART0 21
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#define ESP32C3_PERIPH_UART1 22
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#define ESP32C3_PERIPH_LEDC 23
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#define ESP32C3_PERIPH_EFUSE 24
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#define ESP32C3_PERIPH_TWAI 25
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#define ESP32C3_PERIPH_USB 26
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#define ESP32C3_PERIPH_RTC_CORE 27
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#define ESP32C3_PERIPH_RMT 28
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#define ESP32C3_PERIPH_I2C_EXT0 29
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/* RESERVED interrupts 30-31 */
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#define ESP32C3_PERIPH_TG0_T0 32
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#define ESP32C3_PERIPH_TG0_WDT 33
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#define ESP32C3_PERIPH_TG1_T0 34
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#define ESP32C3_PERIPH_TG1_WDT 35
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/* RESERVED interrupt 36 */
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#define ESP32C3_PERIPH_SYSTIMER_T0 37
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#define ESP32C3_PERIPH_SYSTIMER_T1 38
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#define ESP32C3_PERIPH_SYSTIMER_T2 39
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/* RESERVED interrupts 40-42 */
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#define ESP32C3_PERIPH_APB_ADC 43
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#define ESP32C3_PERIPH_DMA_CH0 44
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#define ESP32C3_PERIPH_DMA_CH1 45
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#define ESP32C3_PERIPH_DMA_CH2 46
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#define ESP32C3_PERIPH_RSA 47
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#define ESP32C3_PERIPH_AES 48
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#define ESP32C3_PERIPH_SHA 49
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#define ESP32C3_PERIPH_FROM_CPU_INT0 50
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#define ESP32C3_PERIPH_FROM_CPU_INT1 51
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#define ESP32C3_PERIPH_FROM_CPU_INT2 52
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#define ESP32C3_PERIPH_FROM_CPU_INT3 53
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#define ESP32C3_PERIPH_ASSIST_DEBUG 54
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#define ESP32C3_PERIPH_DMA_APBPERI_PMS 55
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#define ESP32C3_PERIPH_CORE0_IRAM0_PMS 56
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#define ESP32C3_PERIPH_CORE0_DRAM0_PMS 57
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#define ESP32C3_PERIPH_CORE0_PIF_PMS 58
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#define ESP32C3_PERIPH_CORE0_PIF_PMS_SZIE 59
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/* RESERVED interrupts 60-61 */
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/* Total number of peripherals */
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#define ESP32C3_NPERIPHERALS 62
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/* CPU Interrupts.
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*
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* The ESP32-C3 CPU interrupt controller accepts 31 asynchronous interrupts.
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*/
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#define ESP32C3_NCPUINTS 32
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#define ESP32C3_CPUINT_MAX (ESP32C3_NCPUINTS - 1)
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#define ESP32C3_CPUINT_ALWAYS_RSVD 0
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#define ESP32C3_CPUINT_PERIPHSET 0xffffffff
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/* Reserved CPU interrupt for specific drivers */
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#define ESP32C3_CPUINT_WMAC 1 /* Wi-Fi MAC */
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#define ESP32C3_CPUINT_BT_BB 5 /* BT BB */
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#define ESP32C3_CPUINT_RWBLE 8 /* RW BLE */
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/* IRQ numbers. */
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/* ecall is dispatched like normal interrupts. It occupies an IRQ number. */
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#define RISCV_NIRQ_INTERRUPTS 16 /* Number of RISC-V dispatched interrupts. */
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#define ESP32C3_IRQ_FIRSTPERIPH 16 /* First peripheral IRQ number */
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/* IRQ numbers for peripheral interrupts coming through the Interrupt
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* Matrix.
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*/
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#define ESP32C3_IRQ2PERIPH(irq) ((irq) - ESP32C3_IRQ_FIRSTPERIPH)
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#define ESP32C3_PERIPH2IRQ(id) ((id) + ESP32C3_IRQ_FIRSTPERIPH)
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/* Peripheral IRQs */
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#define ESP32C3_IRQ_WMAC (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_WMAC)
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#define ESP32C3_IRQ_BT_BB (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_BT_BB)
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#define ESP32C3_IRQ_RWBLE (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_RWBLE)
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#define ESP32C3_IRQ_UHCI0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_UHCI0)
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#define ESP32C3_IRQ_GPIO (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_GPIO)
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#define ESP32C3_IRQ_GPIO_NMI (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_GPIO_NMI)
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#define ESP32C3_IRQ_SPI2 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_SPI2)
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#define ESP32C3_IRQ_I2S1 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_I2S1)
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#define ESP32C3_IRQ_UART0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_UART0)
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#define ESP32C3_IRQ_UART1 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_UART1)
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#define ESP32C3_IRQ_LEDC (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_LEDC)
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#define ESP32C3_IRQ_EFUSE (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_EFUSE)
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#define ESP32C3_IRQ_TWAI (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_TWAI)
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#define ESP32C3_IRQ_USB (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_USB)
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#define ESP32C3_IRQ_RTC_CORE (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_RTC_CORE)
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#define ESP32C3_IRQ_RMT (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_RMT)
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#define ESP32C3_IRQ_I2C_EXT0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_I2C_EXT0)
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#define ESP32C3_IRQ_TG0_T0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_TG0_T0)
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#define ESP32C3_IRQ_TG0_WDT (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_TG0_WDT)
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#define ESP32C3_IRQ_TG1_T0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_TG1_T0)
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#define ESP32C3_IRQ_TG1_WDT (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_TG1_WDT)
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#define ESP32C3_IRQ_SYSTIMER_T0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_SYSTIMER_T0)
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#define ESP32C3_IRQ_SYSTIMER_T1 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_SYSTIMER_T1)
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#define ESP32C3_IRQ_SYSTIMER_T2 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_SYSTIMER_T2)
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#define ESP32C3_IRQ_APB_ADC (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_APB_ADC)
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#define ESP32C3_IRQ_DMA_CH0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_DMA_CH0)
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#define ESP32C3_IRQ_DMA_CH1 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_DMA_CH1)
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#define ESP32C3_IRQ_DMA_CH2 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_DMA_CH2)
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#define ESP32C3_IRQ_RSA (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_RSA)
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#define ESP32C3_IRQ_AES (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_AES)
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#define ESP32C3_IRQ_SHA (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_SHA)
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#define ESP32C3_IRQ_FROM_CPU_INT0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_FROM_CPU_INT0)
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#define ESP32C3_IRQ_FROM_CPU_INT1 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_FROM_CPU_INT1)
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#define ESP32C3_IRQ_FROM_CPU_INT2 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_FROM_CPU_INT2)
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#define ESP32C3_IRQ_FROM_CPU_INT3 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_FROM_CPU_INT3)
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#define ESP32C3_IRQ_ASSIST_DEBUG (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_ASSIST_DEBUG)
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#define ESP32C3_IRQ_DMA_APBPERI_PMS (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_DMA_APBPERI_PMS)
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#define ESP32C3_IRQ_CORE0_IRAM0_PMS (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_CORE0_IRAM0_PMS)
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#define ESP32C3_IRQ_CORE0_DRAM0_PMS (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_CORE0_DRAM0_PMS)
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#define ESP32C3_IRQ_CORE0_PIF_PMS (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_CORE0_PIF_PMS)
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#define ESP32C3_IRQ_CORE0_PIF_PMS_SZIE (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_CORE0_PIF_PMS_SZIE)
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#define ESP32C3_NIRQ_PERIPH ESP32C3_NPERIPHERALS
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/* Second level GPIO interrupts. GPIO interrupts are decoded and dispatched
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* as a second level of decoding: The first level dispatches to the GPIO
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* interrupt handler. The second to the decoded GPIO interrupt handler.
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*/
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#ifdef CONFIG_ESP32C3_GPIO_IRQ
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# define ESP32C3_NIRQ_GPIO 22
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# define ESP32C3_FIRST_GPIOIRQ (RISCV_NIRQ_INTERRUPTS + ESP32C3_NIRQ_PERIPH)
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# define ESP32C3_LAST_GPIOIRQ (ESP32C3_FIRST_GPIOIRQ + ESP32C3_NIRQ_GPIO - 1)
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# define ESP32C3_PIN2IRQ(p) ((p) + ESP32C3_FIRST_GPIOIRQ)
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# define ESP32C3_IRQ2PIN(i) ((i) - ESP32C3_FIRST_GPIOIRQ)
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#else
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# define ESP32C3_NIRQ_GPIO 0
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#endif
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#ifdef CONFIG_ESP32C3_RTCIO_IRQ
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/* Second level RTC interrupts. RTC interrupts are decoded and dispatched
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* as a second level of decoding: The first level dispatches to the RTC
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* interrupt handler. The second to the decoded RTC interrupt handler.
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* A third level might be required to be implemented on the driver.
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*/
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# define ESP32C3_NIRQ_RTCIO 9
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# define ESP32C3_FIRST_RTCIOIRQ (RISCV_NIRQ_INTERRUPTS+ESP32C3_NIRQ_PERIPH+ESP32C3_NIRQ_GPIO)
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# define ESP32C3_LAST_RTCIOIRQ (ESP32C3_FIRST_RTCIOIRQ+ESP32C3_NIRQ_RTCIO-1)
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# define ESP32C3_IRQ_RTC_SLP_WAKEUP (ESP32C3_FIRST_RTCIOIRQ+0)
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# define ESP32C3_IRQ_RTC_SLP_REJECT (ESP32C3_FIRST_RTCIOIRQ+1)
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# define ESP32C3_IRQ_RTC_WDT (ESP32C3_FIRST_RTCIOIRQ+2)
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# define ESP32C3_IRQ_RTC_BROWN_OUT (ESP32C3_FIRST_RTCIOIRQ+3)
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# define ESP32C3_IRQ_RTC_MAIN_TIMER (ESP32C3_FIRST_RTCIOIRQ+4)
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# define ESP32C3_IRQ_RTC_SWD (ESP32C3_FIRST_RTCIOIRQ+5)
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# define ESP32C3_IRQ_RTC_XTAL32K_DEAD (ESP32C3_FIRST_RTCIOIRQ+6)
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# define ESP32C3_IRQ_RTC_GLITCH_DET (ESP32C3_FIRST_RTCIOIRQ+7)
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# define ESP32C3_IRQ_RTC_BBPLL_CAL (ESP32C3_FIRST_RTCIOIRQ+8)
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#else
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# define ESP32C3_NIRQ_RTCIO 0
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#endif
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/* Total number of IRQs: ecall + Peripheral IRQs + GPIOs IRQs + RTCIO IRQs. */
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#define NR_IRQS (RISCV_NIRQ_INTERRUPTS + ESP32C3_NIRQ_PERIPH + ESP32C3_NIRQ_GPIO + ESP32C3_NIRQ_RTCIO)
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#endif /* __ARCH_RISCV_INCLUDE_ESP32C3_IRQ_H */
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