288 lines
14 KiB
C
288 lines
14 KiB
C
/****************************************************************************
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* drivers/lcd/tda19988.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* Definitions for the TDA19988.
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* The TDA19988 is a very low power and very small size
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* High-Definition Multimedia Interface (HDMI) 1.4a transmitter
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*/
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#ifndef __DRIVERS_LCD_TDA19988_H
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#define __DRIVERS_LCD_TDA19988_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* CEC Registers ************************************************************/
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/* The device has two I2C interfaces CEC (0x34) and HDMI (0x70). */
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#define CEC_FRO_IM_CLK_CTRL_REG 0xfb
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# define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
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# define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
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#define CEC_STATUS_REG 0xfe
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# define CEC_STATUS_CONNECTED (1 << 1)
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#define CEC_ENAMODS_REG 0xff
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# define CEC_ENAMODS_HDMI (1 << 1)
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# define CEC_ENAMODS_RXSENS (1 << 2)
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# define CEC_ENABLE_ALL 0x87
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/* HDMI Memory Pages ********************************************************/
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/* HDMI Memory is accessed via page and address.
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* The page must first be selected, then only the address is sent in order
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* accessing memory locations within the selected page.
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*/
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#define HDMI_CTRL_PAGE 0x00 /* General control page */
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#define HDMI_PLL_PAGE 0x02 /* PLL settings page */
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#define HDMI_EDID_PAGE 0x09 /* EDID control page */
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#define HDMI_INFO_PAGE 0x10 /* Information frames and packets page */
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#define HDMI_AUDIO_PAGE 0x11 /* Audio settings and content info packets page */
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#define HDMI_HDCPOTP_PAGE 0x12 /* HDCP (TDA19988AHN and TDA19988AET only) and OTP */
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#define HDMI_GAMUT_PAGE 0x13 /* Gamut-related metadata packets page */
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/* The page select register does not lie within the above pages.
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* The value of 0xff is used for this access.
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*/
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#define HDMI_NO_PAGE 0xff
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/* Page-related macros */
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#define MKREG(page, addr) (((page) << 8) | (addr))
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#define REGPAGE(reg) (((reg) >> 8) & 0xff)
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#define REGADDR(reg) ((reg) & 0xff)
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/* General Control Page Registers and Bit Definitions */
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#define HDMI_CTRL_REV_LO_REG MKREG(HDMI_CTRL_PAGE, 0x00)
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#define HDMI_CTRL_MAIN_CNTRL0_REG MKREG(HDMI_CTRL_PAGE, 0x01)
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# define HDMI_CTRL_MAIN_CNTRL0_SR (1 << 0)
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#define HDMI_CTRL_REV_HI_REG MKREG(HDMI_CTRL_PAGE, 0x02)
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# define HDMI_CTRL_REV_TDA9989N2 0x0101 /* Masking out bits 4-5 */
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# define HDMI_CTRL_REV_TDA19989 0x0201
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# define HDMI_CTRL_REV_TDA19989N2 0x0202
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# define HDMI_CTRL_REV_TDA19988 0x0301
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#define HDMI_CTRL_RESET_REG MKREG(HDMI_CTRL_PAGE, 0x0a)
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# define HDMI_CTRL_RESET_AUDIO (1 << 0)
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# define HDMI_CTRL_RESET_I2C (1 << 1)
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#define HDMI_CTRL_DDC_CTRL_REG MKREG(HDMI_CTRL_PAGE, 0x0b)
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# define HDMI_CTRL_DDC_EN 0x00
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#define HDMI_CTRL_DDC_CLK_REG MKREG(HDMI_CTRL_PAGE, 0x0c)
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# define HDMI_CTRL_DDC_CLK_EN (1 << 0)
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#define HDMI_CTRL_INTR_CTRL_REG MKREG(HDMI_CTRL_PAGE, 0x0f)
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# define HDMI_CTRL_INTR_EN_GLO (1 << 2)
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#define HDMI_CTRL_INT_REG MKREG(HDMI_CTRL_PAGE, 0x11)
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# define HDMI_CTRL_INT_EDID (1 << 1)
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#define HDMI_CTRL_VIPCTRL_0_REG MKREG(HDMI_CTRL_PAGE, 0x20)
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#define HDMI_CTRL_VIPCTRL_1_REG MKREG(HDMI_CTRL_PAGE, 0x21)
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#define HDMI_CTRL_VIPCTRL_2_REG MKREG(HDMI_CTRL_PAGE, 0x22)
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#define HDMI_CTRL_VIPCTRL_3_REG MKREG(HDMI_CTRL_PAGE, 0x23)
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# define HDMI_CTRL_VIPCTRL_3_SYNC_HS (2 << 4)
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# define HDMI_CTRL_VIPCTRL_3_V_TGL (1 << 2)
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# define HDMI_CTRL_VIPCTRL_3_H_TGL (1 << 1)
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#define HDMI_CTRL_VIPCTRL_4_REG MKREG(HDMI_CTRL_PAGE, 0x24)
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# define HDMI_CTRL_VIPCTRL_4_BLANKIT_NDE (0 << 2)
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# define HDMI_CTRL_VIPCTRL_4_BLANKIT_HS_VS (1 << 2)
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# define HDMI_CTRL_VIPCTRL_4_BLANKIT_NHS_VS (2 << 2)
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# define HDMI_CTRL_VIPCTRL_4_BLANKIT_HE_VE (3 << 2)
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# define HDMI_CTRL_VIPCTRL_4_BLC_NONE (0 << 0)
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# define HDMI_CTRL_VIPCTRL_4_BLC_RGB444 (1 << 0)
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# define HDMI_CTRL_VIPCTRL_4_BLC_YUV444 (2 << 0)
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# define HDMI_CTRL_VIPCTRL_4_BLC_YUV422 (3 << 0)
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#define HDMI_CTRL_VIPCTRL_5_REG MKREG(HDMI_CTRL_PAGE, 0x25)
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# define HDMI_CTRL_VIPCTRL_5_SP_CNT(n) (((n) & 3) << 1)
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#define HDMI_CTRL_MUX_VP_VIP_OUT_REG MKREG(HDMI_CTRL_PAGE, 0x27)
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#define HDMI_CTRL_MATCTRL_REG MKREG(HDMI_CTRL_PAGE, 0x80)
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# define HDMI_CTRL_MAT_CONTRL_MAT_BP (1 << 2)
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#define HDMI_CTRL_MUX_VIDFORMAT_REG MKREG(HDMI_CTRL_PAGE, 0xa0)
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#define HDMI_CTRL_MUX_REFPIX_MSB_REG MKREG(HDMI_CTRL_PAGE, 0xa1)
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#define HDMI_CTRL_MUX_REFPIX_LSB_REG MKREG(HDMI_CTRL_PAGE, 0xa2)
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#define HDMI_CTRL_MUX_REFLINE_MSB_REG MKREG(HDMI_CTRL_PAGE, 0xa3)
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#define HDMI_CTRL_MUX_REFLINE_LSB_REG MKREG(HDMI_CTRL_PAGE, 0xa4)
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#define HDMI_CTRL_MUX_NPIX_MSB_REG MKREG(HDMI_CTRL_PAGE, 0xa5)
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#define HDMI_CTRL_MUX_NPIX_LSB_REG MKREG(HDMI_CTRL_PAGE, 0xa6)
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#define HDMI_CTRL_MUX_NLINE_MSB_REG MKREG(HDMI_CTRL_PAGE, 0xa7)
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#define HDMI_CTRL_MUX_NLINE_LSB_REG MKREG(HDMI_CTRL_PAGE, 0xa8)
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#define HDMI_CTRL_MUX_VS_LINE_STRT_1_MSB_REG MKREG(HDMI_CTRL_PAGE, 0xa9)
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#define HDMI_CTRL_MUX_VS_LINE_STRT_1_LSB_REG MKREG(HDMI_CTRL_PAGE, 0xaa)
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#define HDMI_CTRL_MUX_VS_PIX_STRT_1_MSB_REG MKREG(HDMI_CTRL_PAGE, 0xab)
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#define HDMI_CTRL_VS_PIX_STRT_1_LSB_REG MKREG(HDMI_CTRL_PAGE, 0xac)
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#define HDMI_CTRL_VS_LINE_END_1_MSB_REG MKREG(HDMI_CTRL_PAGE, 0xad)
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#define HDMI_CTRL_VS_LINE_END_1_LSB_REG MKREG(HDMI_CTRL_PAGE, 0xae)
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#define HDMI_CTRL_VS_PIX_END_1_MSB_REG MKREG(HDMI_CTRL_PAGE, 0xaf)
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#define HDMI_CTRL_VS_PIX_END_1_LSB_REG MKREG(HDMI_CTRL_PAGE, 0xb0)
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#define HDMI_CTRL_VS_LINE_STRT_2_MSB_REG MKREG(HDMI_CTRL_PAGE, 0xb1)
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#define HDMI_CTRL_VS_LINE_STRT_2_LSB_REG MKREG(HDMI_CTRL_PAGE, 0xb2)
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#define HDMI_CTRL_VS_PIX_STRT_2_MSB_REG MKREG(HDMI_CTRL_PAGE, 0xb3)
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#define HDMI_CTRL_VS_PIX_STRT_2_LSB_REG MKREG(HDMI_CTRL_PAGE, 0xb4)
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#define HDMI_CTRL_VS_LINE_END_2_MSB_REG MKREG(HDMI_CTRL_PAGE, 0xb5)
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#define HDMI_CTRL_VS_LINE_END_2_LSB_REG MKREG(HDMI_CTRL_PAGE, 0xb6)
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#define HDMI_CTRL_VS_PIX_END_2_MSB_REG MKREG(HDMI_CTRL_PAGE, 0xb7)
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#define HDMI_CTRL_VS_PIX_END_2_LSB_REG MKREG(HDMI_CTRL_PAGE, 0xb8)
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#define HDMI_CTRL_HS_PIX_START_MSB_REG MKREG(HDMI_CTRL_PAGE, 0xb9)
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#define HDMI_CTRL_HS_PIX_START_LSB_REG MKREG(HDMI_CTRL_PAGE, 0xba)
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#define HDMI_CTRL_HS_PIX_STOP_MSB_REG MKREG(HDMI_CTRL_PAGE, 0xbb)
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#define HDMI_CTRL_HS_PIX_STOP_LSB_REG MKREG(HDMI_CTRL_PAGE, 0xbc)
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#define HDMI_CTRL_VWIN_START_1_MSB_REG MKREG(HDMI_CTRL_PAGE, 0xbd)
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#define HDMI_CTRL_VWIN_START_1_LSB_REG MKREG(HDMI_CTRL_PAGE, 0xbe)
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#define HDMI_CTRL_VWIN_END_1_MSB_REG MKREG(HDMI_CTRL_PAGE, 0xbf)
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#define HDMI_CTRL_VWIN_END_1_LSB_REG MKREG(HDMI_CTRL_PAGE, 0xc0)
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#define HDMI_CTRL_VWIN_START_2_MSB_REG MKREG(HDMI_CTRL_PAGE, 0xc1)
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#define HDMI_CTRL_VWIN_START_2_LSB_REG MKREG(HDMI_CTRL_PAGE, 0xc2)
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#define HDMI_CTRL_VWIN_END_2_MSB_REG MKREG(HDMI_CTRL_PAGE, 0xc3)
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#define HDMI_CTRL_VWIN_END_2_LSB_REG MKREG(HDMI_CTRL_PAGE, 0xc4)
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#define HDMI_CTRL_DE_START_MSB_REG MKREG(HDMI_CTRL_PAGE, 0xc5)
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#define HDMI_CTRL_DE_START_LSB_REG MKREG(HDMI_CTRL_PAGE, 0xc6)
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#define HDMI_CTRL_DE_STOP_MSB_REG MKREG(HDMI_CTRL_PAGE, 0xc7)
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#define HDMI_CTRL_DE_STOP_LSB_REG MKREG(HDMI_CTRL_PAGE, 0xc8)
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#define HDMI_CTRL_TBG_CNTRL_0_REG MKREG(HDMI_CTRL_PAGE, 0xca)
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# define HDMI_CTRL_TBG_CNTRL_0_SYNC_MTHD (1 << 6)
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# define HDMI_CTRL_TBG_CNTRL_0_SYNC_ONCE (1 << 7)
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#define HDMI_CTRL_TBG_CNTRL_1_REG MKREG(HDMI_CTRL_PAGE, 0xcb)
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# define HDMI_CTRL_TBG_CNTRL_1_H_TGL (1 << 0)
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# define HDMI_CTRL_TBG_CNTRL_1_V_TGL (1 << 1)
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# define HDMI_CTRL_TBG_CNTRL_1_TGL_EN (1 << 2)
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# define HDMI_CTRL_TBG_CNTRL_1_DWIN_DIS (1 << 6)
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#define HDMI_CTRL_HVF_CNTRL_0_REG MKREG(HDMI_CTRL_PAGE, 0xe4)
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# define HDMI_CTRL_HVF_CNTRL_0_INTPOL_BYPASS (0 << 0)
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# define HDMI_CTRL_HVF_CNTRL_0_PREFIL_NONE (0 << 2)
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#define HDMI_CTRL_HVF_CNTRL_1_REG MKREG(HDMI_CTRL_PAGE, 0xe5)
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# define HDMI_CTRL_HVF_CNTRL_1_VQR(x) (((x) & 3) << 2)
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# define HDMI_CTRL_HVF_CNTRL_1_VQR_FULL HDMI_CTRL_HVF_CNTRL_1_VQR(0)
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#define HDMI_CTRL_ENABLE_SPACE_REG MKREG(HDMI_CTRL_PAGE, 0xd6)
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#define HDMI_CTRL_RPT_CNTRL_REG MKREG(HDMI_CTRL_PAGE, 0xf0)
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/* PLL Page Registers */
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#define HDMI_PLL_SERIAL_1_REG MKREG(HDMI_PLL_PAGE, 0x00)
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# define HDMI_PLL_SERIAL_1_SRL_MAN_IP (1 << 6)
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#define HDMI_PLL_SERIAL_2_REG MKREG(HDMI_PLL_PAGE, 0x01)
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# define HDMI_PLL_SERIAL_2_SRL_NOSC(x) (((x) & 0x3) << 0)
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# define HDMI_PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4)
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#define HDMI_PLL_SERIAL_3_REG MKREG(HDMI_PLL_PAGE, 0x02)
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# define HDMI_PLL_SERIAL_3_SRL_CCIR (1 << 0)
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# define HDMI_PLL_SERIAL_3_SRL_DE (1 << 2)
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# define HDMI_PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
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#define HDMI_PLL_SERIALIZER_REG MKREG(HDMI_PLL_PAGE, 0x03)
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#define HDMI_PLL_BUFFER_OUT_REG MKREG(HDMI_PLL_PAGE, 0x04)
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#define HDMI_PLL_SCG1_REG MKREG(HDMI_PLL_PAGE, 0x05)
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#define HDMI_PLL_SCG2_REG MKREG(HDMI_PLL_PAGE, 0x06)
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#define HDMI_PLL_SCGN1_REG MKREG(HDMI_PLL_PAGE, 0x07)
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#define HDMI_PLL_SCGN2_REG MKREG(HDMI_PLL_PAGE, 0x08)
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#define HDMI_PLL_SCGR1_REG MKREG(HDMI_PLL_PAGE, 0x09)
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#define HDMI_PLL_SCGR2_REG MKREG(HDMI_PLL_PAGE, 0x0a)
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#define HDMI_PLL_SEL_CLK_REG MKREG(HDMI_PLL_PAGE, 0x11)
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# define HDMI_PLL_SEL_CLK_ENA_SC_CLK (1 << 3)
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# define HDMI_PLL_SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1)
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# define HDMI_PLL_SEL_CLK_SEL_CLK1 (1 << 0)
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#define HDMI_PLL_ANA_GENERAL_REG MKREG(HDMI_PLL_PAGE, 0x12)
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/* EDID Control Page Registers and Bit Definitions */
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#define HDMI_EDID_DATA_REG MKREG(HDMI_EDID_PAGE, 0x00)
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#define HDMI_EDID_REQ_REG MKREG(HDMI_EDID_PAGE, 0xfa)
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# define HDMI_EDID_REQ_READ (1 << 0)
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#define HDMI_EDID_DEV_ADDR_REG MKREG(HDMI_EDID_PAGE, 0xfb)
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# define HDMI_EDID_DEV_ADDR 0xa0
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#define HDMI_EDID_OFFSET_REG MKREG(HDMI_EDID_PAGE, 0xfc)
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# define HDMI_EDID_OFFSET 0x00
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#define HDMI_EDID_SEGM_ADDR_REG MKREG(HDMI_EDID_PAGE, 0xfd)
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#define HDMI_EDID_SEGM_ADDR 0x00
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#define HDMI_EDID_DDC_SEGM_REG MKREG(HDMI_EDID_PAGE, 0xfe)
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# define HDMI_EDID_SEG_ADDR 0x00
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/* HDCP (TDA19988AHN and TDA19988AET only) and OTP Page Registers and Bit
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* Definitions.
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*/
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#define HDMI_HDCPOTP_TX3_REG MKREG(HDMI_HDCPOTP_PAGE, 0x9a)
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#define HDMI_HDCPOTP_TX4_REG MKREG(HDMI_HDCPOTP_PAGE, 0x9b)
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# define HDMI_HDCPOTP_TX4_PDRAM (1 << 1)
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#define HDMI_HDCPOTP_TX33_REG MKREG(HDMI_HDCPOTP_PAGE, 0x9b)
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# define HDMI_HDCPOTP_TX33_HDMI (1 << 1)
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/* Information Frames and Packets Page Registers and Bit Definitions */
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#define HDMI_INFO_VSP MKREG(HDMI_INFO_PAGE, 0x20)
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#define HDMI_INFO_AVI MKREG(HDMI_INFO_PAGE, 0x40)
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#define HDMI_INFO_SPD MKREG(HDMI_INFO_PAGE, 0x60)
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#define HDMI_INFO_AUD MKREG(HDMI_INFO_PAGE, 0x80)
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#define HDMI_INFO_MPS MKREG(HDMI_INFO_PAGE, 0xa0)
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/* Audio settings and content info packets page Registers and Bit
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* Definitions
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*/
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#define HDMI_AUDIO_ENC_CTRL_REG MKREG(HDMI_AUDIO_PAGE, 0x0d)
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# define HDMI_AUDIO_ENC_CNTRL_DVI_MODE (0 << 2)
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# define HDMI_AUDIO_ENC_CNTRL_HDMI_MODE (1 << 2)
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#define HDMI_AUDIO_DIP_IF_FLAGS_REG MKREG(HDMI_AUDIO_PAGE, 0x0f)
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# define HDMI_AUDIO_DIP_IF_FLAGS_IF1 (1 << 1)
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# define HDMI_AUDIO_DIP_IF_FLAGS_IF2 (1 << 2) /* AVI IF on page 10h */
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# define HDMI_AUDIO_DIP_IF_FLAGS_IF3 (1 << 3)
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# define HDMI_AUDIO_DIP_IF_FLAGS_IF4 (1 << 4)
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# define HDMI_AUDIO_DIP_IF_FLAGS_IF5 (1 << 5)
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/* Page Select Register (no page) */
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#define HDMI_PAGE_SELECT_REG MKREG(HDMI_NO_PAGE, 0xff)
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#endif /* __DRIVERS_LCD_TDA19988_H */
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