332 lines
17 KiB
C
332 lines
17 KiB
C
/****************************************************************************
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* include/nuttx/net/gmii.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __INCLUDE_NUTTX_NET_GMII_H
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#define __INCLUDE_NUTTX_NET_GMII_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/net/mii.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* MII register offsets *****************************************************/
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/* Common MII management registers. The IEEE 802.3 standard specifies a
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* register set for controlling and gathering status from the PHY layer. The
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* registers are collectively known as the MII Management registers and are
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* detailed in Section 22.2.4 of the IEEE 802.3 specification.
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*/
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#define GMII_MCR MII_MCR /* GMII management control */
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#define GMII_MSR MII_MSR /* GMII management status */
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#define GMII_PHYID1 MII_PHYID1 /* PHY ID 1 */
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#define GMII_PHYID2 MII_PHYID2 /* PHY ID 2 */
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#define GMII_ADVERTISE MII_ADVERTISE /* Auto-negotiation advertisement */
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#define GMII_LPA MII_LPA /* Auto-negotiation link partner base page ability */
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#define GMII_EXPANSION MII_EXPANSION /* Auto-negotiation expansion */
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#define GMII_NEXTPAGE MII_NEXTPAGE /* Auto-negotiation next page */
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#define GMII_LPANEXTPAGE MII_LPANEXTPAGE /* Auto-negotiation link partner received next page */
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#define GMII_1000BTCR 9 /* 1000BASE-T control */
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#define GMII_1000BTSR 10 /* 1000BASE-T status */
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#define GMII_ERCR 11 /* Extend Register - Control */
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#define GMII_ERDWR 12 /* Extend Register - Data Write Register */
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#define GMII_ERDRR 13 /* Extend Register - Data Read Register */
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#define GMII_ESTATUS MII_ESTATUS /* Extended MII status register */
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/* Extended Registers:
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* Registers 16-31 may be used for vendor specific abilities
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*/
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/* Micrel KSZ9021/31 Vendor Specific Register Addresses *********************/
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#define GMII_KSZ90x1_RLPBK 17 /* Remote loopback, LED mode */
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#define GMII_KSZ90x1_LINKMD 18 /* LinkMD(c) cable diagnostic */
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#define GMII_KSZ90x1_PMAPCS 19 /* Digital PMA/PCS status */
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#define GMII_KSZ90x1_RXERR 21 /* RXER counter */
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#define GMII_KSZ90X1_ICS 27 /* Interrupt control/status */
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#define GMII_KSZ90x1_DBGCTRL1 28 /* Digital debug control 1 */
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#define GMII_KSZ90x1_PHYCTRL 31 /* PHY control */
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/* Micrel KSZ9021/31 Extended Register Addresses */
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#define GMII_KSZ90x1_CCR 256 /* Common control */
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#define GMII_KSZ90x1_SSR 257 /* Strap status */
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#define GMII_KSZ90x1_OMSOR 258 /* Operation mode strap override */
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#define GMII_KSZ90x1_OMSSR 259 /* Operation mode strap status */
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#define GMII_KSZ90X1_RCCPSR 260 /* RGMII clock and control pad skew */
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#define GMII_KSZ90X1_RRDPSR 261 /* RGMII RX data pad skew */
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#define GMII_KSZ90x1_ATR 263 /* Analog test register */
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/* Realtek RTL8211 PHY Extended Registers */
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#define GMII_RTL8211F_NAME "RTL8211F"
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#define GMII_RTL8211F_INER_A42 18 /* Interrupt Enable Register */
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#define GMII_RTL8211F_PHYCR1_A43 24 /* PHY Specific Control Register 1 */
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#define GMII_RTL8211F_PHYCR2_A43 25 /* PHY Specific Control Register 2 */
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#define GMII_RTL8211F_PHYSR_A43 26 /* PHY Specific Status Register */
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#define GMII_RTL8211F_INSR_A43 29 /* Interrupt Status Register */
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#define GMII_RTL8211F_PAGSR 31 /* Page Select Register */
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#define GMII_RTL8211F_PHYSCR_A46 20 /* PHY Special Cofig Register */
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#define GMII_RTL8211F_LCR_D04 16 /* LED Control Register */
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#define GMII_RTL8211F_EEELCR_D04 17 /* EEE LED Control Register */
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#define GMII_RTL8211F_MIICR_D08 21 /* MII Control Register */
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#define GMII_RTL8211F_INTBCR_D40 22 /* INTB Pin Control Register */
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/* MII register bit settings ************************************************/
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/* MII Control register bit definitions */
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#define GMII_MCR_UNIDIR MII_MCR_UNIDIR
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#define GMII_MCR_SPEED1000 MII_MCR_SPEED1000
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#define GMII_MCR_CTST MII_MCR_CTST
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#define GMII_MCR_FULLDPLX MII_MCR_FULLDPLX
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#define GMII_MCR_ANRESTART MII_MCR_ANRESTART
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#define GMII_MCR_ISOLATE MII_MCR_ISOLATE
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#define GMII_MCR_PDOWN MII_MCR_PDOWN
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#define GMII_MCR_ANENABLE MII_MCR_ANENABLE
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#define GMII_MCR_SPEED100 MII_MCR_SPEED100
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#define GMII_MCR_LOOPBACK MII_MCR_LOOPBACK
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#define GMII_MCR_RESET MII_MCR_RESET
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/* MII Status register bit definitions */
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#define GMII_MSR_EXTCAP MII_MSR_EXTCAP
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#define GMII_MSR_JABBERDETECT MII_MSR_JABBERDETECT
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#define GMII_MSR_LINKSTATUS MII_MSR_LINKSTATUS
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#define GMII_MSR_ANEGABLE MII_MSR_ANEGABLE
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#define GMII_MSR_RFAULT MII_MSR_RFAULT
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#define GMII_MSR_ANEGCOMPLETE MII_MSR_ANEGCOMPLETE
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#define GMII_MSR_UNIDIR MII_MSR_UNIDIR
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#define GMII_MSR_MFRAMESUPPRESS MII_MSR_MFRAMESUPPRESS
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#define GMII_MSR_ESTATEN MII_MSR_ESTATEN
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#define GMII_MSR_100BASET2FULL MII_MSR_100BASET2FULL
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#define GMII_MSR_100BASET2HALF MII_MSR_100BASET2HALF
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#define GMII_MSR_10BASETXHALF MII_MSR_10BASETXHALF
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#define GMII_MSR_10BASETXFULL MII_MSR_10BASETXFULL
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#define GMII_MSR_100BASETXHALF MII_MSR_100BASETXHALF
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#define GMII_MSR_100BASETXFULL MII_MSR_100BASETXFULL
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#define GMII_MSR_100BASET4 MII_MSR_100BASET4
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/* MII ID2 register bits */
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#define GMII_PHYID2_REV_SHIFT MII_PHYID2_REV_SHIFT
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#define GMII_PHYID2_REV_MASK MII_PHYID2_REV_MASK
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#define GMII_PHYID2_REV(n) MII_PHYID2_REV(n)
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#define GMII_PHYID2_MODEL_SHIFT MII_PHYID2_MODEL_SHIFT
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#define GMII_PHYID2_MODEL_MASK MII_PHYID2_MODEL_MASK
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# define GMII_PHYID2_MODEL(n) MII_PHYID2_MODEL(n)
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#define GMII_PHYID2_OUI_SHIFT MII_PHYID2_OUI_SHIFT
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#define GMII_PHYID2_OUI_MASK MII_PHYID2_OUI_MASK
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# define GMII_PHYID2_OUI(n) MII_PHYID2_OUI(n)
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/* Advertisement control register bit definitions */
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#define GMII_ADVERTISE_SELECT MII_ADVERTISE_SELECT
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#define GMII_ADVERTISE_CSMA MII_ADVERTISE_CSMA
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#define GMII_ADVERTISE_8023 MII_ADVERTISE_8023
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#define GMII_ADVERTISE_8029 MII_ADVERTISE_8029
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#define GMII_ADVERTISE_8025 MII_ADVERTISE_8025
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#define GMII_ADVERTISE_1394 MII_ADVERTISE_1394
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#define GMII_ADVERTISE_10BASETXHALF MII_ADVERTISE_10BASETXHALF
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#define GMII_ADVERTISE_1000XFULL MII_ADVERTISE_1000XFULL
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#define GMII_ADVERTISE_10BASETXFULL MII_ADVERTISE_10BASETXFULL
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#define GMII_ADVERTISE_1000XHALF MII_ADVERTISE_1000XHALF
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#define GMII_ADVERTISE_100BASETXHALF MII_ADVERTISE_100BASETXHALF
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#define GMII_ADVERTISE_1000XPAUSE MII_ADVERTISE_1000XPAUSE
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#define GMII_ADVERTISE_100BASETXFULL MII_ADVERTISE_100BASETXFULL
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#define GMII_ADVERTISE_1000XASYMPAU MII_ADVERTISE_1000XASYMPAU
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#define GMII_ADVERTISE_100BASET4 MII_ADVERTISE_100BASET4
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#define GMII_ADVERTISE_FDXPAUSE MII_ADVERTISE_FDXPAUSE
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#define GMII_ADVERTISE_ASYMPAUSE MII_ADVERTISE_ASYMPAUSE
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#define GMII_ADVERTISE_RFAULT MII_ADVERTISE_RFAULT
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#define GMII_ADVERTISE_LPACK MII_ADVERTISE_LPACK
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#define GMII_ADVERTISE_NXTPAGE MII_ADVERTISE_NXTPAGE
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/* Link partner ability register bit definitions */
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#define GMII_LPA_SELECT MII_LPA_SELECT
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#define GMII_LPA_CSMA MII_LPA_CSMA
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#define GMII_LPA_8023 MII_LPA_8023
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#define GMII_LPA_8029 MII_LPA_8029
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#define GMII_LPA_8025 MII_LPA_8025
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#define GMII_LPA_8025 MII_LPA_1394
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#define GMII_LPA_1394 MII_LPA_1394
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#define GMII_LPA_10BASETXHALF MII_LPA_10BASETXHALF
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#define GMII_LPA_1000XFULL MII_LPA_1000XFULL
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#define GMII_LPA_1000XFULL MII_LPA_10BASETXFULL
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#define GMII_LPA_10BASETXFULL MII_LPA_10BASETXFULL
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#define GMII_LPA_1000XHALF MII_LPA_1000XHALF
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#define GMII_LPA_100BASETXHALF MII_LPA_100BASETXHALF
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#define GMII_LPA_1000XPAUSE MII_LPA_1000XPAUSE
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#define GMII_LPA_100BASETXFULL MII_LPA_100BASETXFULL
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#define GMII_LPA_1000XASYMPAU MII_LPA_1000XASYMPAU
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#define GMII_LPA_100BASET4 MII_LPA_100BASET4
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#define GMII_LPA_FDXPAUSE MII_LPA_FDXPAUSE
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#define GMII_LPA_ASYMPAUSE MII_LPA_ASYMPAUSE
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#define GMII_LPA_RFAULT MII_LPA_RFAULT
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#define GMII_LPA_LPACK MII_LPA_LPACK
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#define GMII_LPA_NXTPAGE MII_LPA_NXTPAGE
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/* Link partner ability in next page format */
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#define GMII_LPANP_MESSAGE MII_LPANP_MESSAGE
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#define GMII_LPANP_TOGGLE MII_LPANP_TOGGLE
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#define GMII_LPANP_LACK2 MII_LPANP_LACK2
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#define GMII_LPANP_MSGPAGE MII_LPANP_MSGPAGE
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#define GMII_LPANP_LPACK MII_LPANP_LPACK
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#define GMII_LPANP_NXTPAGE MII_LPANP_NXTPAGE
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/* MII Auto-negotiation expansion register bit definitions */
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#define GMII_EXPANSION_ANEGABLE MII_EXPANSION_ANEGABLE
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#define GMII_EXPANSION_PAGERECVD MII_EXPANSION_PAGERECVD
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#define GMII_EXPANSION_ENABLENPAGE MII_EXPANSION_ENABLENPAGE
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#define GMII_EXPANSION_NXTPAGEABLE MII_EXPANSION_NXTPAGEABLE
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#define GMII_EXPANSION_PARFAULTS MII_EXPANSION_PARFAULTS
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/* Auto-negotiation next page advertisement */
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#define GMII_NPADVERTISE_CODE MII_NPADVERTISE_CODE
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#define GMII_NPADVERTISE_TOGGLE MII_NPADVERTISE_TOGGLE
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#define GMII_NPADVERTISE_ACK2 MII_NPADVERTISE_ACK2
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#define GMII_NPADVERTISE_MSGPAGE MII_NPADVERTISE_MSGPAGE
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#define GMII_NPADVERTISE_NXTPAGE MII_NPADVERTISE_NXTPAGE
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/* MMD access control register */
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#define GMII_MMDCONTROL_DEVAD_SHIFT MII_MMDCONTROL_DEVAD_SHIFT
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#define GMII_MMDCONTROL_DEVAD_MASK MII_MMDCONTROL_DEVAD_MASK
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# define GMII_MMDCONTROL_DEVAD(n) MII_MMDCONTROL_DEVAD(n)
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#define GMII_MMDCONTROL_FUNC_SHIFT MII_MMDCONTROL_FUNC_SHIFT
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#define GMII_MMDCONTROL_FUNC_MASK MII_MMDCONTROL_FUNC_MASK
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# define GMII_MMDCONTROL_FUNC_ADDR MII_MMDCONTROL_FUNC_ADDR
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# define GMII_MMDCONTROL_FUNC_NOINCR MII_MMDCONTROL_FUNC_NOINCR
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# define GMII_MMDCONTROL_FUNC_RWINCR MII_MMDCONTROL_FUNC_RWINCR
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# define GMII_MMDCONTROL_FUNC_WINCR MII_MMDCONTROL_FUNC_WINCR
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/* Extended Status Register */
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#define GMII_ESTATUS_1000BASETHALF MII_ESTATUS_1000BASETHALF
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#define GMII_ESTATUS_1000BASETFULL MII_ESTATUS_1000BASETFULL
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#define GMII_ESTATUS_1000BASEXHALF MII_ESTATUS_1000BASEXHALF
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#define GMII_ESTATUS_1000BASEXFULL MII_ESTATUS_1000BASEXFULL
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/* 1000BASE-T Control Register */
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/* Bits 0-7: Reserved */
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#define GMII_1000BTCR_1000BASETHALF (1 << 8) /* Bit 8: 1000Base-T half duplex able */
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#define GMII_1000BTCR_1000BASETFULL (1 << 9) /* Bit 9: 1000Base-T full duplex able */
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#define GMII_1000BTCR_MULTIPLE (1 << 10) /* Bit 10: Port type: Prefer multiport device */
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#define GMII_1000BTCR_MMASTER (1 << 11) /* Bit 11: Configure PHY as master (manual) */
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#define GMII_1000BTCR_MSMC (1 << 12) /* Bit 12: Master/slave manual configuration */
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#define GMII_1000BTCR_TESTMODE_SHIFT (13) /* Bits 13-15: Test Mode */
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#define GMII_1000BTCR_TESTMODE_MASK (7 << GMII_1000BTCR_TESTMODE_SHIFT)
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# define GMII_1000BTCR_MODE_NORMAL (0 << GMII_1000BTCR_TESTMODE_SHIFT)
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# define GMII_1000BTCR_TESTMODE(n) ((uint16_t)(n) << GMII_1000BTCR_TESTMODE_SHIFT) /* n=1-4 */
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/* 1000BASE-T Status Register */
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#define GMII_1000BTSR_IDLERR_SHIFT (0) /* Bits 0-7: Idle error count */
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#define GMII_1000BTSR_IDLERR_MASK (0xff << GMII_1000BTSR_IDLERR_SHIFT)
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/* Bits 8-9: Reserved */
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#define GMII_1000BTSR_LP1000BASETHALF (1 << 10) /* Bit 10: Link partner 1000Base-T half duplex able */
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#define GMII_1000BTSR_LP1000BASETFULL (1 << 11) /* Bit 11: Link partner 1000Base-T full duplex able */
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#define GMII_1000BTSR_RROK (1 << 12) /* Bit 12: Remote receiver OK */
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#define GMII_1000BTSR_LROK (1 << 13) /* Bit 13: Local receiver OK */
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#define GMII_1000BTSR_MASTER (1 << 14) /* Bit 14: Configuration resolved to master */
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#define GMII_1000BTSR_MSFAULT (1 << 15) /* Bit 15: Master/slave fault detected */
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/* Extend Register - Control Register */
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#define GMII_ERCR_ADDR_SHIFT (0) /* Bits 0-7: Select extended register address */
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#define GMII_ERCR_ADDR_MASK (0xff << GMII_ERCR_ADDR_SHIFT)
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# define GMII_ERCR_ADDR(n) ((uint16_t)(n) << GMII_ERCR_ADDR_SHIFT)
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#define GMII_ERCR_PAGE (1 << 8) /* Bit 8: Select page for extended register */
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/* Bits 9-14: Reserved */
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#define GMII_ERCR_READ (0) /* Bit 15: 0=Read extended register */
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#define GMII_ERCR_WRITE (1 << 15) /* Bit 15: 1=Write extended register */
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/* Extend Register - Data Write Register (16-bit data value) */
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/* Extend Register - Data Read Register (16-bit data value) */
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/* Micrel KSZ9021/31 Vendor Specific Register Bit Definitions ***************/
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/* KSZ8021/31 Register 27: Interrupt control/status */
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#define GMII_KSZ90x1_INT_JEN (1 << 15) /* Jabber interrupt enable */
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#define GMII_KSZ90x1_INT_REEN (1 << 14) /* Receive error interrupt enable */
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#define GMII_KSZ90x1_INT_PREN (1 << 13) /* Page received interrupt enable */
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#define GMII_KSZ90x1_INT_PDFEN (1 << 12) /* Parallel detect fault interrupt enable */
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#define GMII_KSZ90x1_INT_LPAEN (1 << 11) /* Link partner acknowledge interrupt enable */
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#define GMII_KSZ90X1_INT_LDEN (1 << 10) /* Link down fault interrupt enable */
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#define GMII_KSZ90x1_INT_RFEN (1 << 9) /* Remote fault interrupt enable */
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#define GMII_KSZ90X1_INT_LUEN (1 << 8) /* Link up interrupt enable */
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#define GMII_KSZ90x1_INT_J (1 << 7) /* Jabber interrupt */
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#define GMII_KSZ90x1_INT_RE (1 << 6) /* Receive error interrupt */
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#define GMII_KSZ90x1_INT_PR (1 << 5) /* Page received interrupt */
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#define GMII_KSZ90x1_INT_PDF (1 << 4) /* Parallel detect fault interrupt */
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#define GMII_KSZ90x1_INT_LPA (1 << 3) /* Link partner acknowledge interrupt */
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#define GMII_KSZ90x1_INT_LD (1 << 2) /* Link down fault interrupt */
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#define GMII_KSZ90x1_INT_RF (1 << 1) /* Remote fault interrupt */
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#define GMII_KSZ90x1_INT_LU (1 << 0) /* Link up interrupt */
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/* RTL8211 register bit settings ********************************************/
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/* RTL8211F MII ID1/2 register bits */
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#define GMII_PHYID1_RTL8211F 0x001c /* ID1 value for Realtek RTL8211F */
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#define GMII_PHYID2_RTL8211F 0xc878 /* ID2 value for Realtek RTL8211F */
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#define GMII_RTL8211F_PHYSR_SPEED_MASK 0x30
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#define GMII_RTL8211F_PHYSR_10MBPS 0x00
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#define GMII_RTL8211F_PHYSR_100MBPS 0x10
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#define GMII_RTL8211F_PHYSR_1000MBPS 0x20
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#define GMII_RTL8211F_PHYSR_DUPLEX 0x8
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/****************************************************************************
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* Type Definitions
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCLUDE_NUTTX_NET_GMII_H */
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