412 lines
10 KiB
C
412 lines
10 KiB
C
/****************************************************************************
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* drivers/spi/ice40.c
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <assert.h>
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#include <debug.h>
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#include <errno.h>
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#include <fcntl.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <nuttx/arch.h>
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#include <nuttx/fs/fs.h>
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#include <nuttx/fs/ioctl.h>
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#include <nuttx/ioexpander/gpio.h>
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#include <nuttx/kmalloc.h>
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#include <nuttx/spi/spi.h>
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#include <nuttx/spi/ice40.h>
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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/* Character driver methods */
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static int ice40_open(FAR struct file *filep);
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static int ice40_close(FAR struct file *filep);
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static ssize_t ice40_read(FAR struct file *filep, FAR char *buffer,
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size_t buflen);
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static ssize_t ice40_write(FAR struct file *filep, FAR const char *buffer,
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size_t buflen);
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static int ice40_ioctl(FAR struct file *filep, int cmd, unsigned long arg);
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/* Helper functions */
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static int ice40_init_fpga(FAR struct ice40_dev_s *dev);
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static int ice40_writeblk(FAR struct ice40_dev_s *dev,
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FAR const char *buffer,
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size_t buflen);
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static int ice40_endwrite(FAR struct ice40_dev_s *dev);
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/****************************************************************************
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* Private Data
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****************************************************************************/
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static const struct file_operations g_ice40_fops =
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{
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ice40_open, /* open */
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ice40_close, /* close */
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ice40_read, /* read */
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ice40_write, /* write */
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NULL, /* seek */
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ice40_ioctl, /* ioctl */
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};
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: ice40_open
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*
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* Description:
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* This function is called whenever the ICE40 device is opened.
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*
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****************************************************************************/
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static int
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ice40_open(FAR struct file *filep)
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{
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FAR struct inode *inode = filep->f_inode;
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FAR struct ice40_dev_s *dev = inode->i_private;
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DEBUGASSERT(dev != NULL);
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if (dev->is_open)
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{
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return -EBUSY;
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}
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dev->is_open = true;
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return OK;
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}
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/****************************************************************************
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* Name: ice40_close
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*
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* Description:
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* This function is called whenever the ICE40 device is closed.
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*
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****************************************************************************/
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static int
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ice40_close(FAR struct file *filep)
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{
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FAR struct inode *inode = filep->f_inode;
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FAR struct ice40_dev_s *dev = inode->i_private;
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DEBUGASSERT(dev != NULL);
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if (dev->in_progress)
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{
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if (ice40_endwrite(dev))
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{
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_err("ERROR: Failed to end writing to FPGA\n");
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dev->is_open = false;
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return -EIO;
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}
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}
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dev->is_open = false;
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return OK;
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}
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/****************************************************************************
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* Name: ice40_configspi
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*
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* Description:
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* Configure the SPI instance for to match the DAT-31R5-SP+
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* specifications
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*
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****************************************************************************/
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static inline void
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ice40_configspi(FAR struct spi_dev_s *spi)
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{
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DEBUGASSERT(spi != NULL);
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/* Configure SPI Mode for the ICE40 */
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SPI_SETMODE(spi, ICE40_SPI_MODE);
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SPI_SETBITS(spi, 8);
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SPI_HWFEATURES(spi, 0);
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SPI_SETFREQUENCY(spi, CONFIG_ICE40_SPI_FREQUENCY);
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}
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/****************************************************************************
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* Name: ice40_init_fpga
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*
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* Description:
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* Initialize the FPGA - set it to SPI Master load mode
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* Reset the FPGA with the CS pin active low
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* and send 8 dummy bits with CS high to start the SPI transfer.
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*
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****************************************************************************/
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static int
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ice40_init_fpga(FAR struct ice40_dev_s *dev)
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{
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DEBUGASSERT(dev != NULL);
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DEBUGASSERT(dev->spi != NULL);
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SPI_LOCK(dev->spi, true);
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ice40_configspi(dev->spi);
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dev->ops->reset(dev, true);
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up_udelay(2);
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dev->ops->select(dev, true);
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up_udelay(2);
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dev->ops->reset(dev, false);
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up_udelay(1200);
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dev->ops->select(dev, false);
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SPI_SEND(dev->spi, 0xff);
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dev->ops->select(dev, true);
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dev->in_progress = true;
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return 0;
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}
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/****************************************************************************
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* Name: ice_v_writeblk
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*
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* Description:
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* Write block to the ICE40 FPGA, max 4096 bytes
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****************************************************************************/
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static inline int
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ice40_writeblk(FAR struct ice40_dev_s *dev, FAR const char *buffer,
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size_t buflen)
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{
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uint32_t nbytes;
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DEBUGASSERT(dev != NULL);
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DEBUGASSERT(dev->spi != NULL);
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DEBUGASSERT(buffer != NULL);
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DEBUGASSERT(buflen > 0);
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if (!dev->in_progress)
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{
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_err("ERROR: FPGA not initialized\n");
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return -EINVAL;
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}
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ice40_configspi(dev->spi);
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while (buflen > 0)
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{
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nbytes = buflen;
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if (nbytes >= ICE_SPI_MAX_XFER)
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{
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nbytes = ICE_SPI_MAX_XFER;
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}
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SPI_SNDBLOCK(dev->spi, buffer, nbytes);
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buffer += nbytes;
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buflen -= nbytes;
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}
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return 0;
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}
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/****************************************************************************
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* Name: ice_v_endwrite
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*
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* Description:
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* End writing bitstream to the ICE40 FPGA
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****************************************************************************/
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static int
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ice40_endwrite(FAR struct ice40_dev_s *dev)
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{
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ice40_configspi(dev->spi);
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int cdone = 0;
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DEBUGASSERT(dev != NULL);
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DEBUGASSERT(dev->spi != NULL);
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if (!dev->in_progress)
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{
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_err("ERROR: FPGA not initialized\n");
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return -EINVAL;
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}
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dev->ops->select(dev, false);
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for (size_t i = 0; i < ICE40_SPI_FINAL_CLK_CYCLES + 7 / 8; i++)
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{
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SPI_SEND(dev->spi, 0xff);
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}
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cdone = dev->ops->get_status(dev);
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if (cdone == 0)
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{
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_err("ERROR: CDONE not high after writing to FPGA\n");
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SPI_LOCK(dev->spi, false);
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return -ENODEV;
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}
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SPI_LOCK(dev->spi, false);
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dev->in_progress = false;
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return 0;
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}
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/****************************************************************************
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* Name: ice40_write
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*
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* Description:
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* Write buffer to the ICE40 FPGA
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****************************************************************************/
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static ssize_t
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ice40_write(FAR struct file *filep, FAR const char *buffer, size_t buflen)
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{
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int ret;
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DEBUGASSERT(buffer != NULL);
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DEBUGASSERT(filep != NULL);
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FAR struct inode *inode = filep->f_inode;
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DEBUGASSERT(inode != NULL);
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FAR struct ice40_dev_s *dev = inode->i_private;
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DEBUGASSERT(dev != NULL);
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DEBUGASSERT(dev->spi != NULL);
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if (!dev->in_progress)
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{
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ret = ice40_init_fpga(dev);
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if (ret < 0)
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{
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_err("ERROR: Failed to initialize FPGA: %d\n", ret);
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return ret;
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}
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}
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ret = ice40_writeblk(dev, buffer, buflen);
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if (ret < 0)
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{
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_err("ERROR: Failed to write to FPGA: %d\n", ret);
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return ret;
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}
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return buflen;
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}
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/****************************************************************************
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* Name: ice40_read
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*
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* Description:
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* Read is ignored.
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****************************************************************************/
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static ssize_t
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ice40_read(FAR struct file *filep, FAR char *buffer, size_t buflen)
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{
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return 0;
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}
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/****************************************************************************
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* Name: ice40_ioctl
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*
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* Description:
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* The only available ICTL is RFIOC_SETATT. It expects a struct
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* attenuator_control* as the argument to set the attenuation
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* level. The channel is ignored as the DAT-31R5-SP+ has just a
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* single attenuator.
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****************************************************************************/
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static int
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ice40_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
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{
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FAR struct inode *inode = filep->f_inode;
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FAR struct ice40_dev_s *dev = inode->i_private;
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int ret = OK;
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switch (cmd)
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{
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case FPGAIOC_WRITE_INIT:
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ret = ice40_init_fpga(dev);
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break;
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case FPGAIOC_WRITE:
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ret = ice40_writeblk(dev, (FAR const char *)arg, sizeof(arg));
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break;
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case FPGAIOC_WRITE_COMPLETE:
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ret = ice40_endwrite(dev);
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break;
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default:
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sninfo("Unrecognized cmd: %d\n", cmd);
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: ice40_register
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*
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* Description:
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* Register the ice_v character device as 'devpath'.
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*
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****************************************************************************/
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int ice40_register(FAR const char *path, FAR struct ice40_dev_s *dev)
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{
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int ret;
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/* Sanity check */
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DEBUGASSERT(dev != NULL);
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/* Register the character driver */
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ret = register_driver(path, &g_ice40_fops, 0666, dev);
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if (ret < 0)
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{
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snerr("ERROR: Failed to register driver: %d\n", ret);
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}
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return ret;
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}
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