114 lines
5.0 KiB
C
114 lines
5.0 KiB
C
/****************************************************************************
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* arch/risc-v/include/fe310/irq.h
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*
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* Copyright (C) 2019 Masayuki Ishikawa. All rights reserved.
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* Author: Masayuki Ishikawa <masayuki.ishikawa@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __ARCH_RISCV_INCLUDE_FE310_IRQ_H
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#define __ARCH_RISCV_INCLUDE_FE310_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <arch/irq.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Map RISC-V exception code to NuttX IRQ */
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/* IRQ 0-15 : (exception:interrupt=0) */
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#define FE310_IRQ_IAMISALIGNED (0) /* Instruction Address Misaligned */
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#define FE310_IRQ_IAFAULT (1) /* Instruction Address Fault */
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#define FE310_IRQ_IINSTRUCTION (2) /* Illegal Instruction */
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#define FE310_IRQ_BPOINT (3) /* Break Point */
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#define FE310_IRQ_LAMISALIGNED (4) /* Load Address Misaligned */
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#define FE310_IRQ_LAFAULT (5) /* Load Access Fault */
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#define FE310_IRQ_SAMISALIGNED (6) /* Store/AMO Address Misaligned */
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#define FE310_IRQ_SAFAULT (7) /* Store/AMO Access Fault */
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#define FE310_IRQ_ECALLU (8) /* Environment Call from U-mode */
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/* 9-10: Reserved */
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#define FE310_IRQ_ECALLM (11) /* Environment Call from M-mode */
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/* 12-15: Reserved */
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/* IRQ 16- : (async event:interrupt=1) */
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#define FE310_IRQ_ASYNC (16)
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#define FE310_IRQ_MSOFT (FE310_IRQ_ASYNC + 3) /* Machine Software Int */
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#define FE310_IRQ_MTIMER (FE310_IRQ_ASYNC + 7) /* Machine Timer Int */
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#define FE310_IRQ_MEXT (FE310_IRQ_ASYNC + 11) /* Machine External Int */
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/* Machine Global External Interrupt */
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#define FE310_IRQ_UART0 (FE310_IRQ_MEXT + 3)
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#define FE310_IRQ_UART1 (FE310_IRQ_MEXT + 4)
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#define FE310_IRQ_GPIO0 (FE310_IRQ_MEXT + 8)
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#define FE310_IRQ_GPIO1 (FE310_IRQ_MEXT + 9)
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#define FE310_IRQ_GPIO2 (FE310_IRQ_MEXT + 10)
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#define FE310_IRQ_GPIO3 (FE310_IRQ_MEXT + 11)
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#define FE310_IRQ_GPIO4 (FE310_IRQ_MEXT + 12)
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#define FE310_IRQ_GPIO5 (FE310_IRQ_MEXT + 13)
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#define FE310_IRQ_GPIO6 (FE310_IRQ_MEXT + 14)
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#define FE310_IRQ_GPIO7 (FE310_IRQ_MEXT + 15)
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#define FE310_IRQ_GPIO8 (FE310_IRQ_MEXT + 16)
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#define FE310_IRQ_GPIO9 (FE310_IRQ_MEXT + 17)
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#define FE310_IRQ_GPIO10 (FE310_IRQ_MEXT + 18)
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#define FE310_IRQ_GPIO11 (FE310_IRQ_MEXT + 19)
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#define FE310_IRQ_GPIO12 (FE310_IRQ_MEXT + 20)
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#define FE310_IRQ_GPIO13 (FE310_IRQ_MEXT + 21)
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#define FE310_IRQ_GPIO14 (FE310_IRQ_MEXT + 22)
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#define FE310_IRQ_GPIO15 (FE310_IRQ_MEXT + 23)
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#define FE310_IRQ_GPIO16 (FE310_IRQ_MEXT + 24)
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#define FE310_IRQ_GPIO17 (FE310_IRQ_MEXT + 25)
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#define FE310_IRQ_GPIO18 (FE310_IRQ_MEXT + 26)
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#define FE310_IRQ_GPIO19 (FE310_IRQ_MEXT + 27)
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#define FE310_IRQ_GPIO20 (FE310_IRQ_MEXT + 28)
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#define FE310_IRQ_GPIO21 (FE310_IRQ_MEXT + 29)
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#define FE310_IRQ_GPIO22 (FE310_IRQ_MEXT + 30)
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#define FE310_IRQ_GPIO23 (FE310_IRQ_MEXT + 31)
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#define FE310_IRQ_GPIO24 (FE310_IRQ_MEXT + 32)
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#define FE310_IRQ_GPIO25 (FE310_IRQ_MEXT + 33)
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#define FE310_IRQ_GPIO26 (FE310_IRQ_MEXT + 34)
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#define FE310_IRQ_GPIO27 (FE310_IRQ_MEXT + 35)
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#define FE310_IRQ_GPIO28 (FE310_IRQ_MEXT + 36)
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#define FE310_IRQ_GPIO29 (FE310_IRQ_MEXT + 37)
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#define FE310_IRQ_GPIO30 (FE310_IRQ_MEXT + 38)
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#define FE310_IRQ_GPIO31 (FE310_IRQ_MEXT + 39)
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/* Total number of IRQs */
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#define NR_IRQS (FE310_IRQ_GPIO31 + 1)
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#endif /* __ARCH_RISCV_INCLUDE_FE310_IRQ_H */
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