40 lines
1.7 KiB
Plaintext
40 lines
1.7 KiB
Plaintext
/****************************************************************************
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* boards/arm/lpc17xx_40xx/pnev5180b/scripts/memory.ld
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* The LPC1769 has 512Kb of FLASH beginning at address 0x0000:0000 and
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* 64Kb of total SRAM: 32Kb of SRAM in the CPU block beginning at address
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* 0x10000000 and 32Kb of AHB SRAM in two banks of 16Kb beginning at addresses
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* 0x20070000 and 0x20080000. Here we assume that .data and .bss will all fit
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* into the 32Kb CPU SRAM address range.
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*/
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MEMORY
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{
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/* 512Kb FLASH - Leave 256Kb for application usage */
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kflash (rx) : ORIGIN = 0x00000000, LENGTH = 128K
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uflash (rx) : ORIGIN = 0x00020000, LENGTH = 128K
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/* 32Kb of SRAM in the CPU block - Leave 32Kb of AHB SRAM for app usage */
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ksram (rwx) : ORIGIN = 0x10000000, LENGTH = 16K
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usram (rwx) : ORIGIN = 0x10004000, LENGTH = 16K
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}
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