75 lines
3.4 KiB
C
75 lines
3.4 KiB
C
/****************************************************************************
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* arch/arm/include/lpc54xx/chip.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_LPC54XX_CHIP_H
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#define __ARCH_ARM_INCLUDE_LPC54XX_CHIP_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Prototypes
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****************************************************************************/
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/* LPC546xx Family Options.
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*
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* Family CPU Flash SRAM FS HS Ether- CAN CAN LCD Package
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* MHz (Kb) (Kb) USB USB net 2.0 FD
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* LPC54628 220 512 200 X X X X X X BGA180
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* LPC54618 180 <=512 <=200 X X X X X X BGA180, LQFP208
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* LPC54616 180 <=512 <=200 X X X X X BGA100, BGA180,
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* LQFP100, LQFP208
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* LPC54608 180 512 200 X X X X X BGA180, LQFP208
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* LPC54607 180 <=512 <=200 X X X BGA180, LQFP208
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* LPC54606 180 <=512 <=200 X X X X BGA100, BGA180,
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* LQFP100, LQFP208
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* LPC54605 180 <=512 <=200 X X BGA180
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*/
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/* NVIC priority levels *****************************************************/
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/* Each priority field holds a priority value, 0-31. The lower the value, the
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* greater the priority of the corresponding interrupt.
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*
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* The Cortex-M4 core supports 8 programmable interrupt priority levels.
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*/
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#define NVIC_SYSH_PRIORITY_MIN 0xe0 /* All bits[7:5] set is minimum priority */
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define NVIC_SYSH_PRIORITY_STEP 0x20 /* Steps between priorities */
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Functions Prototypes
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****************************************************************************/
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#endif /* __ARCH_ARM_INCLUDE_LPC43XX_CHIP_H */
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