89 lines
2.7 KiB
Plaintext
89 lines
2.7 KiB
Plaintext
#
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# For a description of the syntax of this configuration file,
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# see the file kconfig-language.txt in the NuttX tools repository.
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#
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if ARCH_XTENSA
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choice
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prompt "XTENSA architecture selection"
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default ARCH_CHIP_ESP32
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config ARCH_CHIP_ESP32
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bool "Espressif ESP32"
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select ARCH_FAMILY_LX6
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select XTENSA_HAVE_INTERRUPTS
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select ARCH_HAVE_MULTICPU
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select ARCH_HAVE_MODULE_TEXT
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select ARCH_TOOLCHAIN_GNU
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select ARCH_GLOBAL_IRQDISABLE
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---help---
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The ESP32 is a dual-core system from Espressif with two Harvard
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architecture Xtensa LX6 CPUs. All embedded memory, external memory
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and peripherals are located on the data bus and/or the instruction
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bus of these CPUs. With some minor exceptions, the address mapping
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of two CPUs is symmetric, meaning they use the same addresses to
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access the same memory.
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The two CPUs are named "PRO_CPU" and "APP_CPU" (for "protocol" and
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"application"), however for most purposes the two CPUs are
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interchangeable.
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endchoice # XTENSA chip selection
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config ARCH_FAMILY_LX6
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bool
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default n
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---help---
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Cadence® Tensilica® Xtensa® LX6 data plane processing unit (DPU).
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The LX6 is a configurable and extensible processor core.
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config ARCH_CHIP
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string
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default "esp32" if ARCH_CHIP_ESP32
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config XTENSA_CP_LAZY
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bool "Lazy co-processor state restoration"
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default n
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depends on EXPERIMENTAL
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---help---
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NuttX logic saves and restores the co-processor enabled (CPENABLE)
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register on each context switch. This has disadvantages in that (1)
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co-processor context will be saved and restored even if the co-
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processor was never used, and (2) tasks must explicitly enable and
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disable co-processors.
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An alternative, "lazy" co-processor state restore is enabled with
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this option. That logic works like as follows:
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a. CPENABLE is set to zero on each context switch, disabling all co-
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processors.
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b. If/when the task attempts to use the disabled co-processor, an
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exception occurs
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c. The co-processor exception handler re-enables the co-processor.
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config XTENSA_USE_OVLY
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bool
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default n
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---help---
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Enable code overlay support. This option is currently unsupported.
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config XTENSA_CP_INITSET
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hex "Default co-processor enables"
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default 0x0001
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range 0 0xffff
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depends on !XTENSA_CP_LAZY
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---help---
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Co-processors may be enabled on a thread by calling xtensa_coproc_enable()
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and disabled by calling xtensa_coproc_disable(). Some co-processors
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should be enabled on all threads by default. That set of co-processors
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is provided by CONFIG_XTENSA_CP_INITSET. Each bit corresponds to one
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coprocessor with the same bit layout as for the CPENABLE register.
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source arch/xtensa/src/lx6/Kconfig
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if ARCH_CHIP_ESP32
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source arch/xtensa/src/esp32/Kconfig
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endif
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endif # ARCH_XTENSA
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