215 lines
7.5 KiB
C
215 lines
7.5 KiB
C
/****************************************************************************
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* boards/arm/sama5/sama5d3-xplained/include/board_396mhz.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_SAMA5_SAMA5D3_XPLAINED_INCLUDE_BOARD_396MHZ_H
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#define __BOARDS_ARM_SAMA5_SAMA5D3_XPLAINED_INCLUDE_BOARD_396MHZ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* After power-on reset, the SAMA5 device is running on a 12MHz internal RC.
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* These definitions will configure operational clocking.
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*
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* This is the configuration provided in the Atmel example code.
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* This results in a CPU clock of 396MHz:
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*
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* MAINOSC: Frequency = 12MHz (crystal)
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* PLLA: PLL Divider = 1, Multiplier = 66 to generate PLLACK = 792MHz
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* Master Clock (MCK): Source = PLLACK/2, Prescalar = 1, MDIV = 3 to generate
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* MCK = 132MHz
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* CPU clock = 396MHz
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*/
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/* Main oscillator register settings.
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*
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* The start up time should be should be:
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* Start Up Time = 8 * MOSCXTST / SLCK = 56 Slow Clock Cycles.
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*/
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#define BOARD_CKGR_MOR_MOSCXTST (62 << PMC_CKGR_MOR_MOSCXTST_SHIFT) /* Start-up Time */
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/* PLLA configuration.
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*
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* Divider = 1
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* Multipler = 66
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*/
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#define BOARD_CKGR_PLLAR_COUNT (63 << PMC_CKGR_PLLAR_COUNT_SHIFT)
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#define BOARD_CKGR_PLLAR_OUT (0)
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#define BOARD_CKGR_PLLAR_MUL (65 << PMC_CKGR_PLLAR_MUL_SHIFT)
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#define BOARD_CKGR_PLLAR_DIV PMC_CKGR_PLLAR_DIV_BYPASS
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/* PMC master clock register settings.
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*
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* Master/Processor Clock Source Selection = PLLA
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* Master/Processor Clock Prescaler = 1
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* PLLA Divider = 2
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* Master Clock Division (MDIV) = 3
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*
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* NOTE: Bit PLLADIV2 must always be set to 1 when MDIV is set to 3.
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*
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* Prescaler input = 792MHz / 2 = 396MHz
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* Prescaler output = 396MHz / 1 = 396MHz
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* Processor Clock (PCK) = 396MHz
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* Master clock (MCK) = 396MHz / 3 = 132MHz
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*/
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#define BOARD_PMC_MCKR_CSS PMC_MCKR_CSS_PLLA
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#define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV1
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#define BOARD_PMC_MCKR_PLLADIV PMC_MCKR_PLLADIV2
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#define BOARD_PMC_MCKR_MDIV PMC_MCKR_MDIV_PCKDIV3
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/* ADC Configuration
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*
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* ADCClock = MCK / ((PRESCAL+1) * 2)
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*
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* Given:
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* MCK = 132MHz
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* ADCClock = 8MHz
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* Then:
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* PRESCAL = 7.25
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*
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* PRESCAL=7 and MCK=132MHz yields ADC clock of 8.25MHz
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*/
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#define BOARD_ADC_PRESCAL (7)
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#define BOARD_TSD_STARTUP (40) /* 40 nanoseconds */
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#define BOARD_TSD_TRACKTIM (2000) /* Min 1µs at 8MHz */
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#define BOARD_TSD_DEBOUNCE (10000000) /* 10 milliseconds (units nanoseconds) */
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/* Resulting frequencies */
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#define BOARD_MAINCK_FREQUENCY BOARD_MAINOSC_FREQUENCY
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#define BOARD_PLLA_FREQUENCY (792000000) /* PLLACK: 66 * 12Mhz / 1 */
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#define BOARD_PCK_FREQUENCY (396000000) /* CPU: PLLACK / 2 / 1 */
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#define BOARD_MCK_FREQUENCY (132000000) /* MCK: PLLACK / 2 / 1 / 3 */
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#define BOARD_ADCCLK_FREQUENCY (8250000) /* ADCCLK: MCK / ((7+1)*2) */
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/* On some SAMA5's, the clocking to peripherals may be divided down from MCK,
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* but not for the SAMA5D3.
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*/
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#define BOARD_PIT_FREQUENCY BOARD_MCK_FREQUENCY
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#define BOARD_USART_FREQUENCY BOARD_MCK_FREQUENCY
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#if defined(CONFIG_SAMA5_EHCI) || defined(CONFIG_SAMA5_OHCI) || \
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defined(CONFIG_SAMA5_UDPHS)
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/* The USB Host High Speed requires a 480 MHz clock (UPLLCK) for the embedded
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* High-speed transceivers. UPLLCK is the output of the 480 MHz UTMI PLL
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* (UPLL). The source clock of the UTMI PLL is the Main OSC output: Either
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* the 12MHz internal RC oscillator on a an external 12MHz crystal. The
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* Main OSC must be 12MHz because the UPLL has a built-in 40x multiplier.
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*
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* For High-speed operations, the user has to perform the following:
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*
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* 1) Enable UHP peripheral clock, bit (1 << AT91C_ID_UHPHS) in
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* PMC_PCER register.
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* 2) Write CKGR_PLLCOUNT field in PMC_UCKR register.
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* 3) Enable UPLL, bit AT91C_CKGR_UPLLEN in PMC_UCKR register.
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* 4) Wait until UTMI_PLL is locked. LOCKU bit in PMC_SR register
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* 5) Enable BIAS, bit AT91C_CKGR_BIASEN in PMC_UCKR register.
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* 6) Select UPLLCK as Input clock of OHCI part, USBS bit in PMC_USB
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* register.
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* 7) Program the OHCI clocks (UHP48M and UHP12M) with USBDIV field in
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* PMC_USB register. USBDIV must be 9 (division by 10) if UPLLCK is
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* selected.
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* 8) Enable OHCI clocks, UHP bit in PMC_SCER register.
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*
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* Steps 2 through 7 performed here. 1 and 8 are performed in the EHCI
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* driver is initialized.
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*/
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# define BOARD_USE_UPLL 1 /* Use UPLL for clock source */
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# define BOARD_CKGR_UCKR_UPLLCOUNT (15) /* Maximum value */
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# define BOARD_CKGR_UCKR_BIASCOUNT (15) /* Maximum value */
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/* REVISIT: The divisor of 10 produces a rate that is too high. Division
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* by 5, however, seems to work just fine. No idea why?
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*/
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# define BOARD_UPLL_OHCI_DIV (5) /* Divide by 5 */
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#endif
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/* HSMCI clocking
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*
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* Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK)
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* divided by (2*(CLKDIV) + CLOCKODD + 2).
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*
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* MCI_SPEED = MCK / (2*CLKDIV + CLOCKODD + 2)
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*
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* Where CLKDIV has a range of 0-255.
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*/
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/* MCK = 132MHz, CLKDIV = 164,
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* MCI_SPEED = 132MHz / (2*164 + 0 + 2) = 400 KHz
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*/
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#define HSMCI_INIT_CLKDIV (164 << HSMCI_MR_CLKDIV_SHIFT)
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/* MCK = 132MHz, CLKDIV = 2 w/CLOCKODD,
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* MCI_SPEED = 132MHz /(2*2 + 1 + 2) = 18.9 MHz
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*/
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#define HSMCI_MMCXFR_CLKDIV ((2 << HSMCI_MR_CLKDIV_SHIFT) | HSMCI_MR_CLKODD)
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/* MCK = 132MHz, CLKDIV = 2,
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* MCI_SPEED = 132MHz /(2*2 + 0 + 2) = 22 MHz
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*/
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#define HSMCI_SDXFR_CLKDIV (2 << HSMCI_MR_CLKDIV_SHIFT)
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#define HSMCI_SDWIDEXFR_CLKDIV HSMCI_SDXFR_CLKDIV
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* !__ASSEMBLY__ */
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#endif /* __BOARDS_ARM__SAMA5SAMA5D3_XPLAINED_INCLUDE_BOARD_396MHZ_H */
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