197 lines
7.8 KiB
C
197 lines
7.8 KiB
C
/****************************************************************************
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* include/nuttx/analog/ads1242.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __INCLUDE_NUTTX_ANALOG_ADS1242_H
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#define __INCLUDE_NUTTX_ANALOG_ADS1242_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/analog/ioctl.h>
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#include <nuttx/spi/spi.h>
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#if defined(CONFIG_SPI) && defined(CONFIG_ADC_ADS1242)
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* IOCTL Commands ***********************************************************/
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/* Cmd: ANIOC_ADS2142_READ Arg: uint32_t *value
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* Cmd: ANIOC_ADS2142_SET_GAIN Arg: uint8_t value
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* Cmd: ANIOC_ADS2142_SET_POSITIVE_INPUT Arg: uint8_t value
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* Cmd: ANIOC_ADS2142_SET_NEGATIVE_INPUT Arg: uint8_t value
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* Cmd: ANIOC_ADS2142_IS_DATA_READY Arg: bool *value
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* Cmd: ANIOC_ADS2142_DO_SYSTEM_OFFSET_CALIB Arg: None
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*/
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#define ANIOC_ADS2142_READ _ANIOC(AN_ADS2142_FIRST + 0)
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#define ANIOC_ADS2142_SET_GAIN _ANIOC(AN_ADS2142_FIRST + 1)
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#define ANIOC_ADS2142_SET_POSITIVE_INPUT _ANIOC(AN_ADS2142_FIRST + 2)
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#define ANIOC_ADS2142_SET_NEGATIVE_INPUT _ANIOC(AN_ADS2142_FIRST + 3)
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#define ANIOC_ADS2142_IS_DATA_READY _ANIOC(AN_ADS2142_FIRST + 4)
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#define ANIOC_ADS2142_DO_SYSTEM_OFFSET_CALIB _ANIOC(AN_ADS2142_FIRST + 5)
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/* ADS1242 REGISTER *********************************************************/
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#define ADS1242_REG_SETUP (0x00) /* Setup Register */
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#define ADS1242_REG_MUX (0x01) /* Multiplexer Control Register */
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#define ADS1242_REG_ACR (0x02) /* Analog Control Register */
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#define ADS1242_REG_ODAC (0x03) /* Offset DAC */
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#define ADS1242_REG_DIO (0x04) /* Data I/O */
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#define ADS1242_REG_DIR (0x05) /* Direction Control for Data I/O */
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#define ADS1242_REG_IOCON (0x06) /* I/O Configuration Register */
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/* ADS1242 REGISTER Bit Definitions *****************************************/
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/* SETUP */
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#define ADS1242_REG_SETUP_BIT_BOCS (1 << 3)
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#define ADS1242_REG_SETUP_BIT_PGA2 (1 << 2)
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#define ADS1242_REG_SETUP_BIT_PGA1 (1 << 1)
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#define ADS1242_REG_SETUP_BIT_PGA0 (1 << 0)
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/* MUX */
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#define ADS1242_REG_MUX_BIT_PSEL3 (1 << 7)
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#define ADS1242_REG_MUX_BIT_PSEL2 (1 << 6)
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#define ADS1242_REG_MUX_BIT_PSEL1 (1 << 5)
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#define ADS1242_REG_MUX_BIT_PSEL0 (1 << 4)
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#define ADS1242_REG_MUX_BIT_NSEL3 (1 << 3)
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#define ADS1242_REG_MUX_BIT_NSEL2 (1 << 2)
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#define ADS1242_REG_MUX_BIT_NSEL1 (1 << 1)
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#define ADS1242_REG_MUX_BIT_NSEL0 (1 << 0)
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/* ACR */
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#define ADS1242_REG_ACR_BIT_NDRDY (1 << 7)
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#define ADS1242_REG_ACR_BIT_UnB (1 << 6)
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#define ADS1242_REG_ACR_BIT_SPEED (1 << 5)
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#define ADS1242_REG_ACR_BIT_BUFEN (1 << 4)
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#define ADS1242_REG_ACR_BIT_BITORDER (1 << 3)
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#define ADS1242_REG_ACR_BIT_RANGE (1 << 2)
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#define ADS1242_REG_ACR_BIT_DR1 (1 << 1)
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#define ADS1242_REG_ACR_BIT_DR0 (1 << 0)
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/* ADS1242 SPI COMMANDS *****************************************************/
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#define ADS1242_CMD_READ_DATA (0x01)
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#define ADS1242_CMD_READ_REGISTER (0x10)
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#define ADS1242_CMD_WRITE_REGISTER (0x50)
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#define ADS1242_CMD_SELF_OFFSET_CALIB (0xF1)
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#define ADS1242_CMD_SELF_GAIN_CALIB (0xf2)
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#define ADS1242_CMD_SYSTEM_OFFSET_CALIB (0xf3)
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#define ADS1242_CMD_RESET (0xfe)
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/* SPI BUS PARAMETERS *******************************************************/
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/* 100 kHz, SCLK period has to be at least 4 x tOsc period of ADS1242
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* oscillator circuit.
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*/
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#define ADS1242_SPI_FREQUENCY (100000)
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/* Device uses SPI Mode 1: CKPOL = 0, CKPHA = 1 */
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#define ADS1242_SPI_MODE (SPIDEV_MODE1)
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/****************************************************************************
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* Public Types
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****************************************************************************/
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typedef enum
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{
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ADS1242_X1 = 0,
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ADS1242_X2 = ADS1242_REG_SETUP_BIT_PGA0,
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ADS1242_X4 = ADS1242_REG_SETUP_BIT_PGA1,
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ADS1242_X8 = ADS1242_REG_SETUP_BIT_PGA1 | ADS1242_REG_SETUP_BIT_PGA0,
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ADS1242_X16 = ADS1242_REG_SETUP_BIT_PGA2,
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ADS1242_X32 = ADS1242_REG_SETUP_BIT_PGA2 | ADS1242_REG_SETUP_BIT_PGA0,
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ADS1242_X64 = ADS1242_REG_SETUP_BIT_PGA2 | ADS1242_REG_SETUP_BIT_PGA1,
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ADS1242_X128 = ADS1242_REG_SETUP_BIT_PGA2 | ADS1242_REG_SETUP_BIT_PGA1 |
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ADS1242_REG_SETUP_BIT_PGA0
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} ADS1242_GAIN_SELECTION;
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typedef enum
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{
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ADS1242_P_AIN0 = 0,
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ADS1242_P_AIN1 = ADS1242_REG_MUX_BIT_PSEL0,
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ADS1242_P_AIN2 = ADS1242_REG_MUX_BIT_PSEL1,
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ADS1242_P_AIN3 = ADS1242_REG_MUX_BIT_PSEL1 | ADS1242_REG_MUX_BIT_PSEL0,
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ADS1242_P_AIN4 = ADS1242_REG_MUX_BIT_PSEL2,
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ADS1242_P_AIN5 = ADS1242_REG_MUX_BIT_PSEL2 | ADS1242_REG_MUX_BIT_PSEL0,
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ADS1242_P_AIN6 = ADS1242_REG_MUX_BIT_PSEL2 | ADS1242_REG_MUX_BIT_PSEL1,
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ADS1242_P_AIN7 = ADS1242_REG_MUX_BIT_PSEL2 | ADS1242_REG_MUX_BIT_PSEL1 |
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ADS1242_REG_MUX_BIT_PSEL0,
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} ADS1242_POSITIVE_INPUT_SELECTION;
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typedef enum
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{
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ADS1242_N_AIN0 = 0,
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ADS1242_N_AIN1 = ADS1242_REG_MUX_BIT_NSEL0,
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ADS1242_N_AIN2 = ADS1242_REG_MUX_BIT_NSEL1,
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ADS1242_N_AIN3 = ADS1242_REG_MUX_BIT_NSEL1 | ADS1242_REG_MUX_BIT_NSEL0,
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ADS1242_N_AIN4 = ADS1242_REG_MUX_BIT_NSEL2,
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ADS1242_N_AIN5 = ADS1242_REG_MUX_BIT_NSEL2 | ADS1242_REG_MUX_BIT_NSEL0,
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ADS1242_N_AIN6 = ADS1242_REG_MUX_BIT_NSEL2 | ADS1242_REG_MUX_BIT_NSEL1,
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ADS1242_N_AIN7 = ADS1242_REG_MUX_BIT_NSEL2 | ADS1242_REG_MUX_BIT_NSEL1 |
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ADS1242_REG_MUX_BIT_NSEL0,
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} ADS1242_NEGATIVE_INPUT_SELECTION;
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Name: ads1242_register
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*
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* Description:
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* Register the ADS1242 character device as 'devpath'
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*
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* Input Parameters:
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* devpath - The full path to the driver to register. E.g., "/dev/ads1242"
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* spi - An instance of the SPI interface to use to communicate with
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* ADS1242
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* osc_freq_hz - The frequency of the ADS1242 oscillator in Hz. Required
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* for calculating the minimum delay periods when accessing
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* the device via SPI.
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*
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* Returned Value:
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* Zero (OK) on success; a negated errno value on failure.
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*
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****************************************************************************/
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int ads1242_register(FAR const char *devpath, FAR struct spi_dev_s *spi,
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uint32_t const osc_freq_hz);
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* CONFIG_SPI && CONFIG_ADC_ADS1242 */
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#endif /* __INCLUDE_NUTTX_ANALOG_ADS1242_H */
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