263 lines
8.5 KiB
C
263 lines
8.5 KiB
C
/****************************************************************************
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* boards/arm/stm32wb/nucleo-wb55rg/include/nucleo-wb55rg.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_STM32WB_NUCLEO_WB55RG_INCLUDE_NUCLEO_WB55RG_H
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#define __BOARDS_ARM_STM32WB_NUCLEO_WB55RG_INCLUDE_NUCLEO_WB55RG_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* The Nucleo WB55RG supports both HSE and LSE crystals (X1 and X2). As
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* shipped, the HSE is a 32MHz crystal X1. Therefore, the Nucleo WB55RG can
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* run off the HSI clock, or the MSI, or the HSE. Here we configure HSE to
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* give us 64MHz system clock (maximum supported for STM32WB chips)
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*/
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/* HSI - 16 MHz RC factory-trimmed
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* LSI - 32 KHz RC
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* MSI - variable up to 48 MHz, synchronized to LSE
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* HSE - 32 MHz installed
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* LSE - 32.768 kHz installed
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* HSI48 - 48 MHz fine-granularity trimmable RC with CRS
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*/
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#define STM32WB_HSI_FREQUENCY 16000000ul
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#define STM32WB_LSI_FREQUENCY 32000
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#define STM32WB_LSE_FREQUENCY 32768
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#define STM32WB_HSE_FREQUENCY 32000000ul
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/* XXX there needs to be independent selections for the System Clock Mux and
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* the PLL Source Mux; currently System Clock Mux always is PLL, and PLL
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* Source Mux is chosen by the following define. This is probably OK in many
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* cases, but should be separated to support other power configurations.
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*/
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#if 0
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# define HSI_CLOCK_CONFIG 1 /* HSI clock configuration */
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#elif 1
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# define HSE_CLOCK_CONFIG 1 /* HSE with 32MHz xtal */
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#else
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# define MSI_CLOCK_CONFIG 1 /* MSI @ 4MHz autotrimmed via LSE */
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#endif
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#if 0
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# define STM32WB_BOARD_RFWKP_USEHSE 1 /* CPU2 use HSE/1024 on RF wakeup */
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#elif 1
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# define STM32WB_BOARD_RFWKP_USELSE 1 /* CPU2 use LSE on RF wakeup */
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#endif
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#if defined(HSI_CLOCK_CONFIG)
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#define STM32WB_BOARD_USEHSI 1
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#define STM32WB_SYSCLK_FREQUENCY 64000000ul
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/* Prescaler common to all PLL inputs; will be 1 */
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#define STM32WB_PLLCFG_PLLM RCC_PLLCFG_PLLM(1)
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/* 'main' PLL config; we use this to generate our system clock via the R
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* output. We set it up as (((16MHz / 1) * 8) / 2) = 64MHz
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*/
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#define STM32WB_PLLCFG_PLLN RCC_PLLCFG_PLLN(8)
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#define STM32WB_PLLCFG_PLLR_ENABLED
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#define STM32WB_PLLCFG_PLLR RCC_PLLCFG_PLLR(2)
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/* 'SAIPLL1' is not used */
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#define STM32WB_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8)
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/* CLK48 will come from HSI48 */
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#define STM32WB_USE_CLK48 1
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#define STM32WB_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48
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#define STM32WB_HSI48_SYNCSRC SYNCSRC_LSE
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/* Enable LSE oscillator, used automatically trim the HSI48, and for RTC */
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#define STM32WB_USE_LSE 1
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#elif defined(HSE_CLOCK_CONFIG)
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/* Use the HSE */
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#define STM32WB_BOARD_USEHSE 1
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#define STM32WB_SYSCLK_FREQUENCY 64000000ul
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/* Prescaler common to all PLL inputs; will be 2 */
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#define STM32WB_PLLCFG_PLLM RCC_PLLCFG_PLLM(2)
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/* 'main' PLL config; we use this to generate our system clock via the R
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* output. We set it up as (((32MHz / 2) * 12) / 3) = 64MHz
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* And the Q output is set as (((32MHz / 2) * 12) / 4) = 48MHz
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*/
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#define STM32WB_PLLCFG_PLLN RCC_PLLCFG_PLLN(12)
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#define STM32WB_PLLCFG_PLLR_ENABLED
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#define STM32WB_PLLCFG_PLLR RCC_PLLCFG_PLLR(3)
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#define STM32WB_PLLCFG_PLLQ_ENABLED
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#define STM32WB_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4)
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/* 'SAIPLL1' is not used */
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#define STM32WB_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8)
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/* CLK48 will come from the PLLMAIN via the Q output */
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#define STM32WB_USE_CLK48 1
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#define STM32WB_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLMAIN
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#define STM32WB_HSI48_SYNCSRC SYNCSRC_NONE
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/* Enable LSE (for the RTC) */
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#define STM32WB_USE_LSE 1
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#elif defined(MSI_CLOCK_CONFIG)
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/* Use the MSI */
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#define STM32WB_BOARD_USEMSI 1
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#define STM32WB_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M
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#define STM32WB_SYSCLK_FREQUENCY 64000000ul
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/* Prescaler common to all PLL inputs; will be 1 */
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#define STM32WB_PLLCFG_PLLM RCC_PLLCFG_PLLM(1)
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/* 'main' PLL config; we use this to generate our system clock via the R
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* output. We set it up as (((4MHz / 1) * 48) / 3) = 64MHz
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* And the Q output is set as (((4MHz / 1) * 48) / 4) = 48MHz
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*/
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#define STM32WB_PLLCFG_PLLN RCC_PLLCFG_PLLN(48)
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#define STM32WB_PLLCFG_PLLR_ENABLED
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#define STM32WB_PLLCFG_PLLR RCC_PLLCFG_PLLR(3)
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#define STM32WB_PLLCFG_PLLQ_ENABLED
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#define STM32WB_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4)
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/* 'SAIPLL1' is not used */
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#define STM32WB_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8)
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/* CLK48 will come from the PLLMAIN via the Q output */
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#define STM32WB_USE_CLK48 1
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#define STM32WB_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLMAIN
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#define STM32WB_HSI48_SYNCSRC SYNCSRC_NONE
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/* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */
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#define STM32WB_USE_LSE 1
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#endif
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/* AHB clock (HCLK) is SYSCLK (64MHz) */
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#define BOARD_AHB_FREQUENCY STM32WB_SYSCLK_FREQUENCY
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#define STM32WB_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
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#define STM32WB_HCLK_FREQUENCY STM32WB_SYSCLK_FREQUENCY
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/* CPU2 clock (HCLK2) is SYSCLK/2 (32MHz) */
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#define STM32WB_RCC_EXTCFGR_C2HPRE RCC_EXTCFGR_C2HPRE_2
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/* AHB4 clock (HCLK4) is SYSCLK (64MHz) */
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#define STM32WB_RCC_EXTCFGR_SHDHPRE RCC_EXTCFGR_SHDHPRE_1
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/* APB1 clock (PCLK1) is HCLK/1 (64MHz) */
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#define STM32WB_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK1
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#define STM32WB_PCLK1_FREQUENCY (STM32WB_HCLK_FREQUENCY / 1)
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/* APB2 clock (PCLK2) is HCLK/1 (64MHz) */
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#define STM32WB_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK1
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#define STM32WB_PCLK2_FREQUENCY (STM32WB_HCLK_FREQUENCY / 1)
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/* Timer Frequencies, if APB prescaler is set to 1, frequency is same to APBx
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* otherwise frequency is 2xAPBx.
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* Note: TIM1,16,17 are on APB2, TIM2 is on APB1
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*/
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/* Timers driven from APB1 will be the same frequency as PCLK1 */
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#define STM32WB_APB1_TIM2_CLKIN (1 * STM32WB_PCLK1_FREQUENCY)
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/* Timers driven from APB2 will be the same frequency as PCLK2 */
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#define STM32WB_APB2_TIM1_CLKIN (1 * STM32WB_PCLK2_FREQUENCY)
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#define STM32WB_APB2_TIM16_CLKIN (1 * STM32WB_PCLK2_FREQUENCY)
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#define STM32WB_APB2_TIM17_CLKIN (1 * STM32WB_PCLK2_FREQUENCY)
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#define BOARD_TIM1_FREQUENCY STM32WB_APB2_TIM1_CLKIN
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#define BOARD_TIM2_FREQUENCY STM32WB_APB1_TIM2_CLKIN
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#define BOARD_TIM16_FREQUENCY STM32WB_APB2_TIM16_CLKIN
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#define BOARD_TIM17_FREQUENCY STM32WB_APB2_TIM17_CLKIN
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/* Higher SYSCLK reguires more flash wait states. */
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#define BOARD_FLASH_WAITSTATES 3
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __BOARDS_ARM_STM32WB_NUCLEO_WB55RG_INCLUDE_NUCLEO_WB55RG_H */
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