533 lines
19 KiB
C
533 lines
19 KiB
C
/****************************************************************************
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* boards/arm/stm32l4/nucleo-l476rg/include/nucleo-l476rg.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_STM32L4_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_H
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#define __BOARDS_ARM_STM32L4_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#if 1
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# define HSI_CLOCK_CONFIG /* HSI-16 clock configuration */
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#elif 0
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/* Make sure you installed one! */
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# define HSE_CLOCK_CONFIG /* HSE with 8 MHz xtal */
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#else
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# define MSI_CLOCK_CONFIG /* MSI @ 4 MHz autotrimmed via LSE */
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#endif
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/* Clocking *****************************************************************/
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#if defined(HSI_CLOCK_CONFIG)
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/* The NUCLEOL476RG supports both HSE and LSE crystals (X2 and X3). However,
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* as shipped, the X3 crystal is not populated. Therefore the Nucleo-L476RG
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* will need to run off the 16MHz HSI clock, or the 32khz-synced MSI.
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*
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* System Clock source : PLL (HSI)
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* SYSCLK(Hz) : 80000000 Determined by PLL configuration
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* HCLK(Hz) : 80000000 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz)
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* AHB Prescaler : 1 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz)
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* APB1 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE1) (Max 80 MHz)
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* APB2 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE2) (Max 80 MHz)
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* HSI Frequency(Hz) : 16000000 (nominal)
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* PLLM : 1 (STM32L4_PLLCFG_PLLM)
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* PLLN : 10 (STM32L4_PLLCFG_PLLN)
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* PLLP : 0 (STM32L4_PLLCFG_PLLP)
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* PLLQ : 0 (STM32L4_PLLCFG_PLLQ)
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* PLLR : 2 (STM32L4_PLLCFG_PLLR)
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* PLLSAI1N : 12
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* PLLSAI1Q : 4
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* Flash Latency(WS) : 4
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* Prefetch Buffer : OFF
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* 48MHz for USB OTG FS, : Doable if required using PLLSAI1 or MSI
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* SDIO and RNG clock
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*/
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/* HSI - 16 MHz RC factory-trimmed
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* LSI - 32 KHz RC
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* MSI - variable up to 48 MHz, synchronized to LSE
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* HSE - not installed
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* LSE - 32.768 kHz installed
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*/
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#define STM32L4_HSI_FREQUENCY 16000000ul
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#define STM32L4_LSI_FREQUENCY 32000
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#define STM32L4_LSE_FREQUENCY 32768
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#define STM32L4_BOARD_USEHSI 1
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/* XXX sysclk mux = pllclk */
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/* XXX pll source mux = hsi */
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/* REVISIT: Trimming of the HSI and MSI is not yet supported. */
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/* Main PLL Configuration.
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*
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* Formulae:
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*
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* VCO input frequency = PLL input clock frequency / PLLM,
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* 1 <= PLLM <= 8
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* VCO output frequency = VCO input frequency × PLLN,
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* 8 <= PLLN <= 86,
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* frequency range 64 to 344 MHz
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* PLL output P (SAI3) clock frequency = VCO frequency / PLLP,
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* PLLP = 7, or 17,
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* or 0 to disable
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* PLL output Q (48M1) clock frequency = VCO frequency / PLLQ,
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* PLLQ = 2, 4, 6, or 8,
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* or 0 to disable
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* PLL output R (CLK) clock frequency = VCO frequency / PLLR,
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* PLLR = 2, 4, 6, or 8,
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* or 0 to disable
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*
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* PLL output P is used for SAI
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* PLL output Q is used for OTG FS, SDMMC, RNG
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* PLL output R is used for SYSCLK
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* PLLP = 0 (not used)
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* PLLQ = 0 (not used)
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* PLLR = 2
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* PLLN = 10
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* PLLM = 1
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*
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* We will configure like this
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*
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* PLL source is HSI
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*
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* PLL_REF = STM32L4_HSI_FREQUENCY / PLLM
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* = 16,000,000 / 1
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* = 16,000,000
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*
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* PLL_VCO = PLL_REF * PLLN
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* = 16,000,000 * 10
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* = 160,000,000
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*
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* PLL_CLK = PLL_VCO / PLLR
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* = 160,000,000 / 2 = 80,000,000
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* PLL_48M1 = disabled
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* PLL_SAI3 = disabled
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*
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* ----------------------------------------
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*
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* PLLSAI1 Configuration
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*
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* The clock input and M divider are identical to the main PLL.
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* However the multiplier and postscalers are independent.
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* The PLLSAI1 is configured only if CONFIG_STM32L4_SAI1PLL is defined
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*
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* SAI1VCO input frequency = PLL input clock frequency
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* SAI1VCO output frequency = SAI1VCO input frequency × PLLSAI1N,
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* 8 <= PLLSAI1N <= 86,
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* frequency range 64 to 344 MHz
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* SAI1PLL output P (SAI1) clock frequency = SAI1VCO frequency / PLLSAI1P,
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* PLLP = 7, or 17,
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* or 0 to disable
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* SAI1PLL output Q (48M2) clock frequency = SAI1VCO frequency / PLLSAI1Q,
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* PLLQ = 2, 4, 6, or 8,
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* or 0 to disable
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* SAI1PLL output R (ADC1) clock frequency = SAI1VCO frequency / PLLSAI1R,
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* PLLR = 2, 4, 6, or 8,
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* or 0 to disable
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*
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* We will configure like this
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*
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* PLLSAI1 disabled
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*
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* ----------------------------------------
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*
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* PLLSAI2 Configuration
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*
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* The clock input and M divider are identical to the main PLL.
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* However the multiplier and postscalers are independent.
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* The PLLSAI2 is configured only if CONFIG_STM32L4_SAI2PLL is defined
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*
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* SAI2VCO input frequency = PLL input clock frequency
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* SAI2VCO output frequency = SAI2VCO input frequency × PLLSAI2N,
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* 8 <= PLLSAI1N <= 86,
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* frequency range 64 to 344 MHz
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* SAI2PLL output P (SAI2) clock frequency = SAI2VCO frequency / PLLSAI2P,
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* PLLP = 7, or 17,
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* or 0 to disable
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* SAI2PLL output R (ADC2) clock frequency = SAI2VCO frequency / PLLSAI2R,
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* PLLR = 2, 4, 6, or 8,
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* or 0 to disable
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*
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* We will configure like this
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*
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* PLLSAI2 disabled
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*
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* ----------------------------------------
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*
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* TODO:
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* The STM32L is a low power peripheral and all these clocks should be
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* configurable at runtime.
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*
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* ----------------------------------------
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*
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* TODO These clock sources can be configured in Kconfig
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* (this is not a board feature)
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* USART1
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* USART2
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* USART3
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* UART4
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* UART5
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* LPUART1
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* I2C1
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* I2C2
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* I2C3
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* LPTIM1
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* LPTIM2
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* SAI1
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* SAI2
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* CLK48
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* ADC
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* SWPMI
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* DFSDM
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*/
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/* Prescaler common to all PLL inputs; will be 1 (XXX source is implicitly
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* as per comment above HSI) .
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*/
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#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1)
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/* 'main' PLL config; we use this to generate our system clock via the R
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* output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz
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*
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* XXX NOTE:
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* currently the main PLL is implicitly turned on and is implicitly
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* the system clock; this should be configurable since not all
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* applications may want things done this way.
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*/
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#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10)
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#define STM32L4_PLLCFG_PLLP 0
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#undef STM32L4_PLLCFG_PLLP_ENABLED
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#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2
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#define STM32L4_PLLCFG_PLLQ_ENABLED
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#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR(2)
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#define STM32L4_PLLCFG_PLLR_ENABLED
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/* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't
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* do that with the main PLL's N value. We set N = 12, and enable
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* the Q output (ultimately for CLK48) with /4. So,
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* 16 MHz / 1 * 12 / 4 = 48 MHz
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*
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* XXX NOTE: currently the SAIPLL /must/ be explicitly selected in the
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* menuconfig, or else all this is a moot point, and the various 48 MHz
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* peripherals will not work (RNG at present). I would suggest removing
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* that option from Kconfig altogether, and simply making it an option
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* that is selected via a #define here, like all these other params.
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*/
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#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12)
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#define STM32L4_PLLSAI1CFG_PLLP 0
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#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED
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#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4
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#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED
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#define STM32L4_PLLSAI1CFG_PLLR 0
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#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED
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/* 'SAIPLL2' is not used in this application */
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#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8)
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#define STM32L4_PLLSAI2CFG_PLLP 0
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#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED
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#define STM32L4_PLLSAI2CFG_PLLR 0
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#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED
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#define STM32L4_SYSCLK_FREQUENCY 80000000ul
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/* CLK48 will come from PLLSAI1 (implicitly Q) */
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#define STM32L4_USE_CLK48
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#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
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/* enable the LSE oscillator, used automatically trim the MSI, and for RTC */
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#define STM32L4_USE_LSE 1
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/* AHB clock (HCLK) is SYSCLK (80MHz) */
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#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY
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/* APB1 clock (PCLK1) is HCLK/1 (80MHz) */
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#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
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#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1)
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/* Timers driven from APB1 will be twice PCLK1 */
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/* REVISIT : this can be configured */
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#define STM32L4_APB1_TIM2_CLKIN (2 * STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM3_CLKIN (2 * STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM4_CLKIN (2 * STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM5_CLKIN (2 * STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM6_CLKIN (2 * STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM7_CLKIN (2 * STM32L4_PCLK1_FREQUENCY)
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/* APB2 clock (PCLK2) is HCLK (80MHz) */
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#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
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#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1)
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/* Timers driven from APB2 will be twice PCLK2 */
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/* REVISIT : this can be configured */
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#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
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#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
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#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
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#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
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#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
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/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
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* otherwise frequency is 2xAPBx.
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* Note: TIM1,8,15,16,17 are on APB2, others on APB1
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*/
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/* REVISIT : this can be configured */
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/* TODO SDMMC */
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#elif defined(HSE_CLOCK_CONFIG)
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/* Use the HSE */
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#define STM32L4_BOARD_USEHSE 1
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/* XXX sysclk mux = pllclk */
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/* XXX pll source mux = hse */
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/* Prescaler common to all PLL inputs */
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#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1)
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/* 'main' PLL config; we use this to generate our system clock */
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#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(20)
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#define STM32L4_PLLCFG_PLLP 0
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#undef STM32L4_PLLCFG_PLLP_ENABLED
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#define STM32L4_PLLCFG_PLLQ 0
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#undef STM32L4_PLLCFG_PLLQ_ENABLED
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#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2
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#define STM32L4_PLLCFG_PLLR_ENABLED
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/* 'SAIPLL1' is used to generate the 48 MHz clock */
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#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12)
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#define STM32L4_PLLSAI1CFG_PLLP 0
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#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED
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#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2
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#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED
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#define STM32L4_PLLSAI1CFG_PLLR 0
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#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED
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/* 'SAIPLL2' is not used in this application */
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#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8)
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#define STM32L4_PLLSAI2CFG_PLLP 0
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#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED
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#define STM32L4_PLLSAI2CFG_PLLR 0
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#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED
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#define STM32L4_SYSCLK_FREQUENCY 80000000ul
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/* Enable CLK48; get it from PLLSAI1 */
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#define STM32L4_USE_CLK48
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#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
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/* Enable LSE (for the RTC) */
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#define STM32L4_USE_LSE 1
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/* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */
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#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY
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/* Configure the APB1 prescaler */
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#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
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#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
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#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
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/* Configure the APB2 prescaler */
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#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
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#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
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#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
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#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
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#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
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#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
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#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
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#elif defined(MSI_CLOCK_CONFIG)
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/* Use the MSI; frequ = 4 MHz; autotrim from LSE */
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#define STM32L4_BOARD_USEMSI 1
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#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M
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/* XXX sysclk mux = pllclk */
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/* XXX pll source mux = msi */
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/* prescaler common to all PLL inputs */
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#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1)
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/* 'main' PLL config; we use this to generate our system clock */
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#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40)
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#define STM32L4_PLLCFG_PLLP 0
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#undef STM32L4_PLLCFG_PLLP_ENABLED
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#define STM32L4_PLLCFG_PLLQ 0
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#undef STM32L4_PLLCFG_PLLQ_ENABLED
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#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2
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#define STM32L4_PLLCFG_PLLR_ENABLED
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/* 'SAIPLL1' is used to generate the 48 MHz clock */
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#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24)
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#define STM32L4_PLLSAI1CFG_PLLP 0
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#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED
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#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2
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#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED
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||
#define STM32L4_PLLSAI1CFG_PLLR 0
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#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED
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|
||
/* 'SAIPLL2' is not used in this application */
|
||
|
||
#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8)
|
||
#define STM32L4_PLLSAI2CFG_PLLP 0
|
||
#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED
|
||
#define STM32L4_PLLSAI2CFG_PLLR 0
|
||
#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED
|
||
|
||
#define STM32L4_SYSCLK_FREQUENCY 80000000ul
|
||
|
||
/* Enable CLK48; get it from PLLSAI1 */
|
||
|
||
#define STM32L4_USE_CLK48
|
||
#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
|
||
|
||
/* Enable LSE (for the RTC) */
|
||
|
||
#define STM32L4_USE_LSE 1
|
||
|
||
/* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */
|
||
|
||
#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
|
||
#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY
|
||
|
||
/* Configure the APB1 prescaler */
|
||
|
||
#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
|
||
#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
|
||
|
||
#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
|
||
#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
|
||
#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
|
||
#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
|
||
#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
|
||
#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
|
||
|
||
/* Configure the APB2 prescaler */
|
||
|
||
#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
|
||
#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
|
||
|
||
#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
|
||
#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
|
||
#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
|
||
#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
|
||
#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY)
|
||
|
||
#endif
|
||
|
||
/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
|
||
* otherwise frequency is 2xAPBx.
|
||
* Note: TIM1,8,15,16,17 are on APB2, others on APB1
|
||
*/
|
||
|
||
#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY
|
||
#define BOARD_TIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
|
||
#define BOARD_TIM3_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
|
||
#define BOARD_TIM4_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
|
||
#define BOARD_TIM5_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
|
||
#define BOARD_TIM6_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
|
||
#define BOARD_TIM7_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
|
||
#define BOARD_TIM8_FREQUENCY STM32L4_HCLK_FREQUENCY
|
||
#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY
|
||
#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY
|
||
#define BOARD_TIM17_FREQUENCY STM32L4_HCLK_FREQUENCY
|
||
#define STM32L4_LPTIM1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
|
||
#define STM32L4_LPTIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2)
|
||
|
||
/****************************************************************************
|
||
* Public Data
|
||
****************************************************************************/
|
||
|
||
#ifndef __ASSEMBLY__
|
||
|
||
#undef EXTERN
|
||
#if defined(__cplusplus)
|
||
#define EXTERN extern "C"
|
||
extern "C"
|
||
{
|
||
#else
|
||
#define EXTERN extern
|
||
#endif
|
||
|
||
/****************************************************************************
|
||
* Public Function Prototypes
|
||
****************************************************************************/
|
||
|
||
#undef EXTERN
|
||
#if defined(__cplusplus)
|
||
}
|
||
#endif
|
||
|
||
#endif /* __ASSEMBLY__ */
|
||
#endif /* __BOARDS_ARM_STM32L4_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_H */
|