411 lines
15 KiB
C
411 lines
15 KiB
C
/****************************************************************************
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* boards/arm/samd2l2/circuit-express/include/board.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_SAMD2L2_CIRCUIT_EXPRESS_INCLUDE_BOARD_H
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#define __BOARDS_ARM_SAMD2L2_CIRCUIT_EXPRESS_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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# ifdef CONFIG_SAMD2L2_GPIOIRQ
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# include <arch/irq.h>
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# endif
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* Overview
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*
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* OSC8M Output = 8MHz
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* `- GCLK1 Input = 8MHz Prescaler = 1 output = 8MHz
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* `- DFLL Input = 8MHz Multiplier = 6 output = 48MHz
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* `- GCLK0 Input = 48MHz Prescaler = 1 output = 48MHz
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* `- PM Input = 48Mhz CPU divider = 1 CPU frequency = 48MHz
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* APBA divider = 1 APBA frequency = 48MHz
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* APBB divider = 1 APBB frequency = 48MHz
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* APBC divider = 1 APBC frequency = 48MHz
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*
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*/
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/* XOSC Configuration -- Not available
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*
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* BOARD_XOSC_ENABLE - Boolean (defined / not defined)
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* BOARD_XOSC_FREQUENCY - In Hz
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* BOARD_XOSC_STARTUPTIME - See SYSCTRL_XOSC_STARTUP_* definitions
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* BOARD_XOSC_ISCRYSTAL - Boolean (defined / not defined)
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* BOARD_XOSC_AMPGC - Boolean (defined / not defined)
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* BOARD_XOSC_ONDEMAND - Boolean (defined / not defined)
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* BOARD_XOSC_RUNINSTANDBY - Boolean (defined / not defined)
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*/
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#undef BOARD_XOSC_ENABLE
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#define BOARD_XOSC_FREQUENCY 12000000UL
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#define BOARD_XOSC_STARTUPTIME SYSCTRL_XOSC_STARTUP_1S
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#define BOARD_XOSC_ISCRYSTAL 1
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#define BOARD_XOSC_AMPGC 1
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#define BOARD_XOSC_ONDEMAND 1
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#undef BOARD_XOSC_RUNINSTANDBY
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/* XOSC32 Configuration -- Not used
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*
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* BOARD_XOSC32K_ENABLE - Boolean (defined / not defined)
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* BOARD_XOSC32K_FREQUENCY - In Hz
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* BOARD_XOSC32K_STARTUPTIME - See SYSCTRL_XOSC32K_STARTUP_* definitions
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* BOARD_XOSC32K_ISCRYSTAL - Boolean (defined / not defined)
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* BOARD_XOSC32K_AAMPEN - Boolean (defined / not defined)
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* BOARD_XOSC32K_EN1KHZ - Boolean (defined / not defined)
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* BOARD_XOSC32K_EN32KHZ - Boolean (defined / not defined)
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* BOARD_XOSC32K_ONDEMAND - Boolean (defined / not defined)
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* BOARD_XOSC32K_RUNINSTANDBY - Boolean (defined / not defined)
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*/
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#undef BOARD_XOSC32K_ENABLE
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#define BOARD_XOSC32K_FREQUENCY 32768 /* 32.768KHz XTAL */
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#define BOARD_XOSC32K_STARTUPTIME SYSCTRL_XOSC32K_STARTUP_2S
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#define BOARD_XOSC32K_ISCRYSTAL 1
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#define BOARD_XOSC32K_AAMPEN 1
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#undef BOARD_XOSC32K_EN1KHZ
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#define BOARD_XOSC32K_EN32KHZ 1
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#define BOARD_XOSC32K_ONDEMAND 1
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#undef BOARD_XOSC32K_RUNINSTANDBY
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/* OSC32 Configuration -- not used
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*
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* BOARD_OSC32K_ENABLE - Boolean (defined / not defined)
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* BOARD_OSC32K_FREQUENCY - In Hz
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* BOARD_OSC32K_STARTUPTIME - See SYSCTRL_OSC32K_STARTUP_* definitions
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* BOARD_OSC32K_EN1KHZ - Boolean (defined / not defined)
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* BOARD_OSC32K_EN32KHZ - Boolean (defined / not defined)
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* BOARD_OSC32K_ONDEMAND - Boolean (defined / not defined)
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* BOARD_OSC32K_RUNINSTANDBY - Boolean (defined / not defined)
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*/
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#undef BOARD_OSC32K_ENABLE
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#define BOARD_OSC32K_FREQUENCY 32768 /* 32.768kHz internal oscillator */
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#define BOARD_OSC32K_STARTUPTIME SYSCTRL_OSC32K_STARTUP_4MS
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#define BOARD_OSC32K_EN1KHZ 1
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#define BOARD_OSC32K_EN32KHZ 1
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#define BOARD_OSC32K_ONDEMAND 1
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#undef BOARD_OSC32K_RUNINSTANDBY
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/* OSC8M Configuration -- always enabled
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*
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* BOARD_OSC8M_PRESCALER - See SYSCTRL_OSC8M_PRESC_DIV* definitions
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* BOARD_OSC8M_ONDEMAND - Boolean (defined / not defined)
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* BOARD_OSC8M_RUNINSTANDBY - Boolean (defined / not defined)
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*/
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#define BOARD_OSC8M_PRESCALER SYSCTRL_OSC8M_PRESC_DIV1
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#define BOARD_OSC8M_ONDEMAND 1
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#undef BOARD_OSC8M_RUNINSTANDBY
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#define BOARD_OSC8M_FREQUENCY 8000000 /* 8MHz high-accuracy internal oscillator */
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/* OSCULP32K Configuration -- not used. */
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#define BOARD_OSCULP32K_FREQUENCY 32000 /* 32kHz ultra-low-power internal oscillator */
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/* Digital Frequency Locked Loop configuration. In closed-loop mode, the
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* DFLL output frequency (Fdfll) is given by:
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*
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* Fdfll = DFLLmul * Frefclk
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* = 6 * 8000000 = 48MHz
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*
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* Where the reference clock is Generic Clock Channel 0 output of GLCK1.
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* GCLCK1 provides OSC8M, undivided.
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*
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* When operating in open-loop mode, the output frequency of the DFLL will
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* be determined by the values written to the DFLL Coarse Value bit group
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* and the DFLL Fine Value bit group in the DFLL Value register.
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*
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* BOARD_DFLL_OPENLOOP - Boolean (defined / not defined)
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* BOARD_DFLL_TRACKAFTERFINELOCK - Boolean (defined / not defined)
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* BOARD_DFLL_KEEPLOCKONWAKEUP - Boolean (defined / not defined)
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* BOARD_DFLL_ENABLECHILLCYCLE - Boolean (defined / not defined)
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* BOARD_DFLL_QUICKLOCK - Boolean (defined / not defined)
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* BOARD_DFLL_ONDEMAND - Boolean (defined / not defined)
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*
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* Closed loop mode only:
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* BOARD_DFLL_GCLKGEN - GCLK index
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* BOARD_DFLL_MULTIPLIER - Value
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* BOARD_DFLL_MAXCOARSESTEP - Value
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* BOARD_DFLL_MAXFINESTEP - Value
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*
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* BOARD_DFLL_FREQUENCY - The resulting frequency
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*/
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#define BOARD_DFLL_ENABLE 1
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#define BOARD_DFLL_OPENLOOP 1
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#undef BOARD_DFLL_ONDEMAND
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#undef BOARD_DFLL_RUNINSTANDBY
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/* DFLL closed loop mode configuration */
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#define BOARD_DFLL_SRCGCLKGEN 1
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#define BOARD_DFLL_MULTIPLIER 6
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#define BOARD_DFLL_QUICKLOCK 1
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#define BOARD_DFLL_TRACKAFTERFINELOCK 1
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#define BOARD_DFLL_KEEPLOCKONWAKEUP 1
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#define BOARD_DFLL_ENABLECHILLCYCLE 1
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#define BOARD_DFLL_MAXCOARSESTEP (0x1f / 4)
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#define BOARD_DFLL_MAXFINESTEP (0xff / 4)
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#define BOARD_DFLL_FREQUENCY (48000000)
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/* GCLK Configuration
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*
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* Global enable/disable.
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*
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* BOARD_GCLK_ENABLE - Boolean (defined / not defined)
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*
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* For n=1-7:
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* BOARD_GCLKn_ENABLE - Boolean (defined / not defined)
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*
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* For n=0-8:
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* BOARD_GCLKn_RUN_IN_STANDBY - Boolean (defined / not defined)
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* BOARD_GCLKn_CLOCK_SOURCE - See GCLK_GENCTRL_SRC_* definitions
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* BOARD_GCLKn_PRESCALER - Value
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* BOARD_GCLKn_OUTPUT_ENABLE - Boolean (defined / not defined)
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*/
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#define BOARD_GCLK_ENABLE 1
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/* GCLK generator 0 (Main Clock) - Source is the DFLL */
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#undef BOARD_GCLK0_RUN_IN_STANDBY
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#define BOARD_GCLK0_CLOCK_SOURCE GCLK_GENCTRL_SRC_DFLL48M
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#define BOARD_GCLK0_PRESCALER 1
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#undef BOARD_GCLK0_OUTPUT_ENABLE
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#define BOARD_GCLK0_FREQUENCY (BOARD_DFLL_FREQUENCY / BOARD_GCLK0_PRESCALER)
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/* Configure GCLK generator 1 - Drives the DFLL */
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#define BOARD_GCLK1_ENABLE 1
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#undef BOARD_GCLK1_RUN_IN_STANDBY
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#define BOARD_GCLK1_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC8M
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#define BOARD_GCLK1_PRESCALER 1
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#undef BOARD_GCLK1_OUTPUT_ENABLE
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#define BOARD_GCLK1_FREQUENCY (BOARD_OSC8M_FREQUENCY / BOARD_GCLK1_PRESCALER)
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/* Configure GCLK generator 2 (RTC) */
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#undef BOARD_GCLK2_ENABLE
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#undef BOARD_GCLK2_RUN_IN_STANDBY
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#define BOARD_GCLK2_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC32K
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#define BOARD_GCLK2_PRESCALER 32
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#undef BOARD_GCLK2_OUTPUT_ENABLE
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#define BOARD_GCLK2_FREQUENCY (BOARD_OSC8M_FREQUENCY / BOARD_GCLK2_PRESCALER)
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/* Configure GCLK generator 3 */
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#undef BOARD_GCLK3_ENABLE
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#undef BOARD_GCLK3_RUN_IN_STANDBY
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#define BOARD_GCLK3_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC8M
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#define BOARD_GCLK3_PRESCALER 1
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#undef BOARD_GCLK3_OUTPUT_ENABLE
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#define BOARD_GCLK3_FREQUENCY (BOARD_OSC8M_FREQUENCY / BOARD_GCLK3_PRESCALER)
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/* Configure GCLK generator 4 */
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#undef BOARD_GCLK4_ENABLE
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#undef BOARD_GCLK4_RUN_IN_STANDBY
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#define BOARD_GCLK4_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC8M
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#define BOARD_GCLK4_PRESCALER 1
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#undef BOARD_GCLK4_OUTPUT_ENABLE
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#define BOARD_GCLK4_FREQUENCY (BOARD_OSC8M_FREQUENCY / BOARD_GCLK4_PRESCALER)
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/* Configure GCLK generator 5 */
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#undef BOARD_GCLK5_ENABLE
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#undef BOARD_GCLK5_RUN_IN_STANDBY
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#define BOARD_GCLK5_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC8M
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#define BOARD_GCLK5_PRESCALER 1
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#undef BOARD_GCLK5_OUTPUT_ENABLE
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#define BOARD_GCLK5_FREQUENCY (BOARD_OSC8M_FREQUENCY / BOARD_GCLK5_PRESCALER)
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/* Configure GCLK generator 6 */
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#undef BOARD_GCLK6_ENABLE
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#undef BOARD_GCLK6_RUN_IN_STANDBY
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#define BOARD_GCLK6_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC8M
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#define BOARD_GCLK6_PRESCALER 1
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#undef BOARD_GCLK6_OUTPUT_ENABLE
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#define BOARD_GCLK6_FREQUENCY (BOARD_OSC8M_FREQUENCY / BOARD_GCLK6_PRESCALER)
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/* Configure GCLK generator 7 */
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#undef BOARD_GCLK7_ENABLE
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#undef BOARD_GCLK7_RUN_IN_STANDBY
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#define BOARD_GCLK7_CLOCK_SOURCE GCLK_GENCTRL_SRC_OSC8M
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#define BOARD_GCLK7_PRESCALER 1
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#undef BOARD_GCLK7_OUTPUT_ENABLE
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#define BOARD_GCLK7_FREQUENCY (BOARD_OSC8M_FREQUENCY / BOARD_GCLK7_PRESCALER)
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/* The source of the main clock is always GCLK_MAIN. Also called GCLKGEN[0],
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* this is the clock feeding the Power Manager.
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* The Power Manager, in turn, generates main clock which is divided down to
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* produce the CPU, AHB, and APB clocks.
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*
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* The main clock is initially OSC8M divided by 8.
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*/
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#define BOARD_GCLK_MAIN_FREQUENCY BOARD_GCLK0_FREQUENCY
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/* Main clock dividers
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*
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* BOARD_CPU_DIVIDER - See PM_CPUSEL_CPUDIV_* definitions
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* BOARD_CPU_FREQUENCY - In Hz
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* BOARD_CPU_FAILDECT - Boolean (defined / not defined)
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* BOARD_APBA_DIVIDER - See M_APBASEL_APBADIV_* definitions
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* BOARD_APBA_FREQUENCY - In Hz
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* BOARD_APBB_DIVIDER - See M_APBBSEL_APBBDIV_* definitions
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* BOARD_APBB_FREQUENCY - In Hz
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* BOARD_APBC_DIVIDER - See M_APBCSEL_APBCDIV_* definitions
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* BOARD_APBC_FREQUENCY - In Hz
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*/
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#define BOARD_CPU_FAILDECT 1
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#define BOARD_CPU_DIVIDER PM_CPUSEL_CPUDIV_1
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#define BOARD_APBA_DIVIDER PM_APBASEL_APBADIV_1
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#define BOARD_APBB_DIVIDER PM_APBBSEL_APBBDIV_1
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#define BOARD_APBC_DIVIDER PM_APBCSEL_APBCDIV_1
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/* Resulting frequencies */
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#define BOARD_MCK_FREQUENCY (BOARD_GCLK_MAIN_FREQUENCY)
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#define BOARD_CPU_FREQUENCY (BOARD_MCK_FREQUENCY)
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#define BOARD_PBA_FREQUENCY (BOARD_MCK_FREQUENCY)
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#define BOARD_PBB_FREQUENCY (BOARD_MCK_FREQUENCY)
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#define BOARD_PBC_FREQUENCY (BOARD_MCK_FREQUENCY)
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#define BOARD_PBD_FREQUENCY (BOARD_MCK_FREQUENCY)
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/* FLASH wait states
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*
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* Vdd Range Wait states Maximum Operating Frequency
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* ------------- -------------- ---------------------------
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* 1.62V to 2.7V 0 14 MHz
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* 1 28 MHz
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* 2 42 MHz
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* 3 48 MHz
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* 2.7V to 3.63V 0 24 MHz
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* 1 48 MHz
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*/
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#if 0 /* REVISIT -- should not be necessary */
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# define BOARD_FLASH_WAITSTATES 1
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#else
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# define BOARD_FLASH_WAITSTATES 2
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#endif
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/* SERCOM definitions *******************************************************/
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/* This is the source clock generator for the GCLK_SERCOM_SLOW clock that is
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* common to all SERCOM modules.
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*/
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#define BOARD_SERCOM05_SLOW_GCLKGEN 0
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/* SERCOM5 USART used to Serial Console
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*
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* PIN PORT SERCOM FUNCTION
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* --- ------------------ -----------
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* 7 PB08 SERCOM4 PAD0 USART TXD
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* 8 PB09 SERCOM4 PAD1 USART RXD
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*/
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#define BOARD_SERCOM4_GCLKGEN 0
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#define BOARD_SERCOM4_SLOW_GCLKGEN BOARD_SERCOM05_SLOW_GCLKGEN
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#define BOARD_SERCOM4_MUXCONFIG (USART_CTRLA_RXPAD1 | USART_CTRLA_TXPAD0_1)
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#define BOARD_SERCOM4_PINMAP_PAD0 PORT_SERCOM4_PAD0_3 /* USART 4 TXD */
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#define BOARD_SERCOM4_PINMAP_PAD1 PORT_SERCOM4_PAD1_3 /* USART 4 RXD */
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#define BOARD_SERCOM4_PINMAP_PAD2 0
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#define BOARD_SERCOM4_PINMAP_PAD3 0
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#define BOARD_SERCOM4_FREQUENCY BOARD_GCLK0_FREQUENCY
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/* USB definitions **********************************************************/
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/* This is the source clock generator for the GCLK_USB clock
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*/
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#define BOARD_USB_GCLKGEN 0
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#define BOARD_USB_FREQUENCY BOARD_GCLK0_FREQUENCY
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/* default USB Pad calibration (not used yet by USB driver) */
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#define BOARD_USB_PADCAL_P 29
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#define BOARD_USB_PADCAL_N 5
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#define BOARD_USB_PADCAL_TRIM 3
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/* LED definitions **********************************************************/
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/* There are 2 LEDs on board the Adafruit Circuit Express board in addition
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* to the neopixel LEDs.
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* The power ON LED which is connected to the 3.3V rail.
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* D13 which is an active high user status LED.
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*
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* This user LED is controlled by PA17.
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*/
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/* LED index values for use with board_userled() */
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#define BOARD_STATUS_LED 0
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#define BOARD_NLEDS 1
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/* LED bits for use with board_userled_all() */
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#define BOARD_STATUS LED_BIT (1 << BOARD_STATUS_LED)
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/* When CONFIG_ARCH_LEDS is defined in the NuttX configuration, NuttX will
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* control the LED as defined below. Thus if the LED is statically on, NuttX
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* has successfully booted and is, apparently, running normally.
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* If the LED is flashing at approximately 2Hz, then a fatal error
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* has been detected and the system has halted.
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*/
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#define LED_STARTED 0 /* STATUS LED=OFF */
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#define LED_HEAPALLOCATE 0 /* STATUS LED=OFF */
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#define LED_IRQSENABLED 0 /* STATUS LED=OFF */
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#define LED_STACKCREATED 1 /* STATUS LED=ON */
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#define LED_INIRQ 2 /* STATUS LED=no change */
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#define LED_SIGNAL 2 /* STATUS LED=no change */
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#define LED_ASSERTION 2 /* STATUS LED=no change */
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#define LED_PANIC 3 /* STATUS LED=flashing */
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/* Button definitions *******************************************************/
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/* Mechanical buttons:
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*
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* The Adafruit Circuit Express contains 2 mechanical buttons and a switch.
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*/
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#define NUM_BUTTONS 3
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#endif /* __BOARDS_ARM_SAMD2L2_CIRCUIT_EXPRESS_INCLUDE_BOARD_H */
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