86 lines
4.0 KiB
Plaintext
86 lines
4.0 KiB
Plaintext
/****************************************************************************
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* boards/arm/lpc17xx_40xx/lpc4088-quickstart/scripts/memory.ld
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* The LPC4088 has 512Kb of FLASH beginning at address 0x0000:0000 and
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* 96KB of total SRAM: 64KB of SRAM in the CPU block beginning at address
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* 0x10000000 and 32Kb of Peripheral SRAM in two banks, 8KB at addresses
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* 0x20000000 bank0 first and 8KB at 0x20002000 at bank0 second. And 16KB
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* at 0x20004000 on bank1.
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*
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* For MPU support, the kernel-mode NuttX section is assumed to be 256KB of
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* FLASH and 4KB of SRAM. That, of course, can be optimized as needed (See
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* also boards/arm/lpc17xx_40xx/lpc4088-quickstart/scripts/kernel-space.ld);
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* 256KB is probably much more than is needed by the RTOS!
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* That size is selected only because it is available due to alignment issues
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* for the user space FLASH memory.
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*
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* Alignment of the user space FLASH partition is a critical factor: The
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* user space FLASH partition will be spanned with a single region of size
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* 2**n bytes. The alignment of the user-space region must be the same. As
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* a consequence, as the user-space increases in size, the alignment
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* requirement also increases.
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*
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* This alignment requirement means that the largest user space FLASH region
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* you can have will be 256KB at it would have to be positioned at
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* 0x00400000. If you change this address, don't forget to change the
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* CONFIG_NUTTX_USERSPACE configuration setting to match and to modify
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* the check in kernel/userspace.c.
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*
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* For the same reasons, the maximum size of the SRAM mapping is limited to
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* 4KB. Both of these alignment limitations could be reduced by using
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* multiple regions to map the FLASH/SDRAM range or perhaps with some
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* clever use of subregions.
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*
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* A detailed memory map for the 64KB CPU SRAM region is as follows:
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*
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* 0x10000 0000: Kernel .data region. Typical size: 0.1KB
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* ------- ---- Kernel .bss region. Typical size: 1.8KB
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* 0x10000 0800: Kernel IDLE thread stack (approximate). Size is
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* determined by CONFIG_IDLETHREAD_STACKSIZE and
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* adjustments for alignment. Typical is 1KB.
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* ------- ---- Padded to 4KB
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* 0x10000 1000: User .data region. Size is variable.
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* ------- ---- User .bss region Size is variable.
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* ------- ---- Beginning of kernel heap. Size determined by
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* CONFIG_MM_KERNEL_HEAPSIZE.
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* 0x10000 8000: Beginning of user heap. Can vary with other settings.
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* 0x10001 0000: End+1 of CPU RAM
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*/
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MEMORY
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{
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/* 256Kb FLASH */
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kflash (rx) : ORIGIN = 0x00000000, LENGTH = 256K /* More than needed */
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uflash (rx) : ORIGIN = 0x00040000, LENGTH = 256K
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/* 64Kb of SRAM in the CPU block */
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ksram (rwx) : ORIGIN = 0x10000000, LENGTH = 4K /* May include waste */
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usram (rwx) : ORIGIN = 0x10001000, LENGTH = 4K
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xsram (rwx) : ORIGIN = 0x10002000, LENGTH = 24K /* All used as heap */
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/* Other peripheral memory (free, nothing is linked here) */
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ahbram8_b0a(rwx) : ORIGIN = 0x20000000, LENGTH = 8K
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ahbram8_b0b(rwx) : ORIGIN = 0x20002000, LENGTH = 8K
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ahbram16(rwx) : ORIGIN = 0x20004000, LENGTH = 16K
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}
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