1105cf0669
IRQs cannot be individually disabled on the eZ80, so using `up_disable_irq()` had no effect. This left the IRQ handler being constantly triggered without the lower half handler running. The macro for EMAC stats was incompatible with Clang. The simplified form gives identical results under ZDS-II. The MII clock speed must be set before trying to read MII registers. It's now done before resetting the PHY using the Mode Control Register. MII initialization waited on the auto-neogotiate restart bit being set but PHY hardware is frequently fast enough to have cleared the bit before the first read of it. It now instead just waits on auto-negotiate completing. The MII poll loop now uses `up_mdelay` because it was far too fast at 50MHz using a busy loop, giving time for a link to be established. Bad packets are now processed enough to release their buffers back to the EMAC hardware. A few typos, unused variables, and other miscellaneous issues were also fixed. |
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