Eero Nurkkala 737d4bf418 risc-v/mpfs: emmcsd: enforce HS DDR mode ... Previously, address 0x03b70000u was written with shift bits that only changed the bit width, not the mode. HS mode is changed via 0x03B90100, which is required, according to Jedec specs, for DDR mode. HS mode was not applied before. Enforce DDR mode (50 MHz) for now. The real boost, however, comes from removing the DMA limitation at 0x08xxxxxx address space, which now seems unnecessary. Signed-off-by: Eero Nurkkala <eero.nurkkala@offcode.fi>		2024-09-25 23:58:08 +08:00
..
include	arch: use up_current_regs/up_set_current_regs replace CURRENT_REGS	2024-09-13 23:18:58 +08:00
src	risc-v/mpfs: emmcsd: enforce HS DDR mode	2024-09-25 23:58:08 +08:00
CMakeLists.txt	cmake:init RISC-V cmake qemu-rv build	2023-10-26 21:01:46 +08:00
Kconfig	risc-v: Add a new option to control exception reason	2024-09-17 15:26:06 -03:00