hujun5 4cb419866f arch: inline up_testset in arm arm64 riscv xtensa ... test: Configuring NuttX and compile: $ ./tools/configure.sh -l qemu-armv8a:nsh_smp $ make Running with qemu $ qemu-system-aarch64 -cpu cortex-a53 -smp 4 -nographic \ -machine virt,virtualization=on,gic-version=3 \ -net none -chardev stdio,id=con,mux=on -serial chardev:con \ -mon chardev=con,mode=readline -kernel ./nuttx Signed-off-by: hujun5 <hujun5@xiaomi.com>		2024-08-21 01:45:10 +08:00
..
esp32	esp32/irq: Allow IRAM ISRs to run during SPI flash operation	2023-11-10 09:11:35 +08:00
esp32s2	xtensa/esp32s2: Add support to TWAI/CANBus controller	2023-09-28 09:35:08 +08:00
esp32s3	esp32s3: add simple boot support	2024-04-17 19:43:05 +08:00
lx6	…
lx7	xtensa: Add initial support for ESP32-S3	2022-01-27 13:46:50 -03:00
xtensa	Indent the define statement by two spaces	2023-05-21 09:52:08 -03:00
.gitignore	…
arch.h	xtensa/esp32s3: Disable psram as task stack	2023-11-08 16:25:57 -03:00
elf.h	…
inttypes.h	…
irq.h	comments/docs: fix typos in comments	2024-03-06 13:31:50 +08:00
limits.h	arch: Define WCHAR_[MIN|MAX] in arch/include/limits.h	2022-06-03 22:25:49 +03:00
loadstore.h	…
setjmp.h	…
simcall.h	…
spinlock.h	arch: inline up_testset in arm arm64 riscv xtensa	2024-08-21 01:45:10 +08:00
stdarg.h	…
syscall.h	xtensa: Add missing input operand on sys_call6 inline ASM	2022-05-18 15:46:57 +02:00
types.h	types.h: fix windows build error	2024-08-14 22:36:57 +08:00